Moog MSD Servo Drive Series, Помощь по устройству, Страница: 67 / 320

SSI encoder basics and requirements
The SSI interface on the MSD Servo Drive has been designed as an actual motor
feedback interface. Accordingly, the connected SSI encoder must meet the following
criteria:

Clock and data inactive level = HIGH

The current position must be internally stored at the first falling clock edge

No lengthened calculation time (in first cycle)

With the first rising clock edge, the encoder must shift the data to the first
position bit to be transmitted (MSB)

1 Mbps rate

Data coding = Binary or Gray

Reading data after the data bits end is permissible

125 µs cycle (i.e. internal position refresh rate
≪
125 µs)

Monoflop time ≥ 6 µs

Data lines driven with logic 0 during monoflop time

No parity bit

No error bits or other status bits

≤14 MultiTurn bits
MOOG
ID No.: CB40859-001 Date: 02/2018
MSD Servo Drive - Device Help
67
6 Encoder
SSI wire break monitoring (bit monitoring during monoflop time)
If monitoring is enabled, the drive, as the SSI clock master, will read data for one
more clock cycle after the data bits (reading data after the data bits end is
permissible). The bit that the master reads in addition to the data bits this way comes
from the SSI encoder’s monoflop time. At the time corresponding to this bit, the SSI
encoder must drive the data lines with a logic 0. If the data lines on connector X7 are
open, a logic 1 will be read here. The bit monitoring at this point makes it possible to
determine whether the SSI data lines are being actively driven with a logic 0 at this
point (no “wire break”) or are not (“wire break”). SSI wire break monitoring can be
disabled by setting P 546[0] - ENC_CH1_Mode to 0001h.
Mode parameters and CycleCount parameters
P 546[0] - ENC_CH1_Mode can be used to run a parity evaluation after the data. In
addition, ENC_CH1_Mode makes it possible to run special SSI encoders that deliver
one or more special bits after the data. In this case, the MSD Servo Drive will not
evaluate these bits – this mode is meant to make it possible to work with SSI
encoders that require for these bits to be sampled. P 616[0] - ENC_CH1_
CycleCount makes it possible to run slower SSI encoders that cannot handle the
required cycle of 125 µs. The control characteristics will deteriorate when using this
type of SSI encoder, and for that reason it is
not recommended.
ID Index Name Unit Description
505 0 ENC_CH1_Sel = 2 =SSI(2)
543 0 ENC_CH1_MultiT Number of MultiTurn bits (absolute encoder)
544 0 ENC_CH1_SingleT Number of SingleTurn bits (absolute encoder)
545 0 ENC_CH1_Code Code selection (SSI absolute encoder)
546 0 ENC_CH1_Mode Mode selection (SSI absolute encoder)
547 0 ENC_CH1_MTBase Minimum MultiTurn position (SSI absolute
encoder)
548 0 ENC_CH1_MTEnable Channel 1: Multi-turn as single-turn
598 0 ENC_CH1_Position inc Position encoder channel 1
616 0 ENC_CH1_CycleCount Channel 1: Position encoder sampling cycle (n x
125 µsec)
Table 6.12: Encoder configuration channel 1 (X7) - SSI parameters