T e c h n i c a l I n f o r m a t i o n
OWNER’S HANDBOOK 5-29
Table B CPU and Memory Module Connectors J8J1, J9J1, J6J1, & J7J1
(continued on next page)
Pin
Signal
Pin
Signal
1
FLSHREQ# (reserved)
2
DISABLEX#
3
I2C_SDA
4
VSS [no connection]
5
VSS
6
I2C_SCL
7
MEMREQ# (reserved)
8
SMI#
9
MEMACK#
10
VSS
11
VCC
12
TDO
13
Reserved
14
Reserved
15
VCC
16
VSS
17
Reserved
18
Reserved
19
ID1 (pull down)
20
ID0 (pull-up)
21
TDI
22
VSS
23
TMS
24
TRST#
25
SPID1#
26
TCLK
27
VSS
28
SPID0#
29
PICCLK
30
VSS
31
PICD0
32
PICD1
33
SNPINV#
34
SHARED# (CFG16#)
35
VSS
36
BACKOFF#
37
MBS64#
38
VSS
39
APAR
40
SBS64#
41
VSS
42
BUSCHK
43
APPERR_E# (CFG17#)
44
VSS
45
DPERR_E#
46
APERR_O#
47
VSS
48
DPERR_O#
49
DP2
50
VSS
51
DP0
52
DP3
53
VSS
54
DP1
55
MBE6#
56
VSS
57
MBE4#
58
MBE7#
59
VSS
60
MBE5#
61
DEFER#
62
NACK#
63
VSS
64
STAT3
65
HRDRES
66
VSS
67
GRNTx#
68
SFTRES
69
REQx#
70
OP64#
71
VCC
72
SEL10/11# (CSEL0#)
73
ALW20M#
74
SMIACT#
75
Reserved
76
RSNPXER#
77
FLUSH#
78
VSS
79
SYNC#
80
IRQ13B/A (CFG12/11#)
81
INTR
82
NMI
83
VCC
84
MODIFIED#
85
SPRDYx# (CFG14/13#)
86
SSTB#
87
WT/WB# (CFG1#)
88
WPROT#
89
ALLOC# (CFG6#)
90
VSS
91
CSB# (CFG7#)
92
CCEN# (CFG0#)
93
LOCK#
94
RESP0# (CFG8#)
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