T e c h n i c a l I n f o r m a t i o n
OWNER’S HANDBOOK 5-25
IDE Header J9F1 (G)
Pin
Signal
Pin
Signal
1
IDERST (reset)
21
IDEDRQ (DMA request 3)
2
GND (ground)
22
GND (ground)
3
ID7 (data bit 7)
23
IDEIOW (I/O write)
4
ID8 (data bit 8)
24
GND (ground)
5
ID6 (data bit 6)
25
IDEIOR (I/O read)
6
ID9 (data bit 9)
26
GND (ground)
7
ID5 (data bit 5)
27
CHRDY (I/O channel ready)
8
ID10 (data bit 10)
28
SPSYNC (address latch
enable)
9
ID4 (data bit 4)
29
IDEDAK (DMA acknowledge 3)
10
ID11 (data bit 11)
30
GND (ground)
11
ID3 (data bit 3)
31
IDEIRQ14 (interrupt request 14)
12
ID12 (data bit 12)
32
IDEIO16 (I/O channel size 16)
13
ID2 (data bit 2)
33
IDESA1 (address bit 1)
14
ID13 (data bit 13)
34
PDIAG
15
ID1 (data bit 1)
35
IDESA0 (address bit 0)
16
ID14 (data bit 14)
36
IDESA2 (address bit 2)
17
ID0 (data bit 0)
37
IDECSO (host chip select 0)
18
ID15 (data bit 15)
38
IDECS1 (host chip select 1)
19
GND (ground)
39
IDEHDACT/DRVPRES (disk
activity/drive present)
20
KEYED (pin
missing)
40
GND (ground)
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