8224 N/B Maintenance
8224 N/B Maintenance
92
5.2 Intel ICH7-M South Bridge (3)
Other Clock
Name Type
Description
CLK14
I
Oscillator Clock:
This clock is used for 8254 timers. It runs at 14.31818 MHz. This
clock is permitted to stop during S3 (or lower) states.
CLK48
I
48 MHz Clock:
This clock is used to run the USB controller. Runs at 48.000 MHz.
This clock is permitted to stop during S3 (or lower) states.
SATA_CLKP
SATA_CLKN
I
100 MHz Differential Clock:
These signals are used to run the SATA controller at 100 MHz. This
clock is permitted to stop during S3/S4/S5 states.
DMI_CLKP,
DMI_CLKN
I
100 MHz Differential Clock:
These signals are used to run the Direct Media Interface. Runs at 100
MHz.
Platform LAN Connect Interface Signals
Name Type
Description
LAN_CLK
I
LAN I/F Clock:
This signal is driven by the Platform LAN Connect component. The
frequency range is 5 MHz to 50 MHz.
LAN_RXD[2:0]
I
Received Data:
The Platform LAN Connect component uses these signals to transfer
data and control information to the integrated LAN controller. These
signals have integrated weak pull-up resistors.
LAN_TXD[2:0]
O
Transmit Data:
The integrated LAN controller uses these signals to transfer data and
control information to the Platform LAN Connect component.
LAN_RSTSYNC
O
LAN Reset/Sync:
The Platform LAN Connect component’s Reset and Sync signals are
multiplexed onto this pin.
Serial ATA Interface Signals (Continued)
Name Type
Description
SATA3GP/
GPIO37
I
Serial ATA 3 General Purpose:
Same function as SATA0GP, except for SATA Port 3.
If interlock switches are not required, this pin can be configured as
GPIO37.
SATALED#
OC
Serial ATA LED:
This is an open-collector output pin driven during SATA command
activity. It is to be connected to external circuitry that can provide the
current to drive a platform LED. When active, the LED is on. When
tri-stated, the LED is off. An external pull-up resistor to Vcc3_3 is
required.
NOTE:
An internal pull-up is enabled only during PLTRST#
assertion.
SATACLKREQ
#/GPIO35
OD
(Native)/
I/O (GP)
Serial ATA Clock Request:
This is an open-drain output pin when configured as
SATACLKREQ#. It is to connect to the system clock chip. When
active, request for SATA Clock running is asserted. When tri-stated,
it tells the Clock Chip that SATA Clock can be stopped. An external
pull-up resistor is required.
Serial Peripheral Interface (SPI) Signals
Name Type
Description
SPI_CS#
I/O
SPI Chip Select:
Also used as the SPI bus request signal.
SPI_MISO
I
SPI Master IN Slave OUT:
Data input pin for Intel
®
ICH7.
SPI_MOSI
O
SPI Master OUT Slave IN:
Data output pin for ICH7.
SPI _ARB
I
SPI Arbitration:
SPI arbitration signal is used to arbitrate the SPI bus with Intel PRO
82573E Gigabit Ethernet Controller when Shared Flash is
implemented.
SPI_CLK
O
SPI Clock:
SPI clock signal, during idle the bus owner will drive the clock signal
low. 17.86 MHz.
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