8224 N/B Maintenance
8224 N/B Maintenance
98
5.2 Intel ICH7-M South Bridge (9)
Power and Ground Signals
Name
Description
Vcc3_3
3.3 V supply for core well I/O buffers (22 pins). This power may be shut off in S3,
S4, S5 or G3 states.
Vcc1_05
1.05 V supply for core well logic (20 pins). This power may be shut off in S3, S4,
S5 or G3 states.
Vcc1_5_A
1.5 V supply for Logic and I/O (30 pins). This power may be shut off in S3, S4, S5
or G3 states.
Vcc1_5_B
1.5 V supply for Logic and I/O (53 pins). This power may be shut off in S3, S4, S5
or G3 states.
V5REF
Reference for 5 V tolerance on core well inputs (2 pins). This power may be shut
off in S3, S4, S5 or G3 states.
VccSus3_3
3.3 V supply for resume well I/O buffers (24 pins). This power is not expected to
be shut off unless the system is unplugged in desktop configurations.
VccSus1_05
1.05 V supply for resume well logic (5 pins). This power is not expected to be shut
off unless the system is unplugged in desktop configurations.
This voltage may be generated internally (see
Function Straps
for strapping
option). If generated internally, these pins should not be connected to an external
supply.
V5REF_Sus
Reference for 5 V tolerance on resume well inputs (1 pin). This power is not
expected to be shut off unless the system is unplugged in desktop configurations.
VccRTC
3.3 V (can drop to 2.0 V min. in G3 state) supply for the RTC well (1 pin). This
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
Note:
Implementations should not attempt to clear CMOS by using a jumper to
pull VccRTC low. Clearing CMOS in an Intel
®
ICH7-based platform can be done
by using a jumper on RTCRST# or GPI.
VccUSBPLL
1.5 V supply for core well logic (1 pin). This signal is used for the USB PLL. This
power may be shut off in S3, S4, S5 or G3 states. Must be powered even if USB
not used.
VccDMIPLL
1.5 V supply for core well logic (1 pins. This signal is used for the DMI PLL. This
power may be shut off in S3, S4, S5 or G3 states.
VccSATAPLL
1.5 V supply for core well logic (1 pins). This signal is used for the SATA PLL.
This power may be shut off in S3, S4, S5 or G3 states. Must be powered even if
SATA not used.
V_CPU_IO
Powered by the same supply as the processor I/O voltage (3 pins). This supply is
used to drive the processor interface signals listed in
Process Interface Signals
.
Vss
Grounds (194 pins).
AC’97/Intel® High Definition Auto Link Signals
Name Type
Description
ACZ_RST#
O
AC’97/Intel® High Definition Audio Reset:
Master hardware reset to external codec(s).
ACZ_SYNC
O
AC ’97/Intel High Definition Audio Sync:
48 kHz fixed rate sample sync to the codec(s). Also used to encode
the stream number.
ACZ_BIT_CLK
I/O
AC ’97 Bit Clock Input:
12.288 MHz serial data clock generated by the external codec(s). This
signal has an integrated pull-down resistor (see Note below).
Intel High Definition Audio Bit Clock Output:
24.000 MHz serial data clock generated by the Intel High Definition
Audio controller (the Intel
®
ICH7). This signal has an integrated
pull-down resistor so that ACZ_BIT_CLK doesn’t float when an Intel
High Definition Audio codec (or no codec) is connected but the
signals are temporarily configured as AC ’97.
ACZ_SDOUT
O
AC ’97/Intel High Definition Audio Serial Data Out:
Serial TDM data output to the codec(s). This serial output is
double-pumped for a bit rate of 48 Mb/s for Intel High Definition
Audio.
NOTE:
ACZ_SDOUT is sampled at the rising edge of PWROK as a
functional strap. See
Function Straps
for more details. There is a weak
integrated pull-down resistor on the ACZ_SDOUT pin.
ACZ_SDIN[2:0]
I
AC ’97/Intel High Definition Audio Serial Data In [2:0]:
Serial TDM data inputs from the three codecs. The serial input is
single-pumped for a bit rate of 24 Mb/s for Intel
®
High Definition
Audio. These signals have integrated pulldown resistors, which are
always enabled.
LPC Interface Signals
Name Type
Description
LAD[3:0]
/
FWH[3:0]
I/O
LPC Multiplexed Command, Address, Data:
For LAD[3:0], internal pull-ups are provided.
LFRAME#
/
FWH4
O
LPC Frame:
LFRAME# indicates the start of an LPC cycle, or an abort.
LDRQ[0]#
LDRQ[1]#/
GPIO23
I
LPC Serial DMA/Master Request Inputs:
LDRQ[1:0]# are used to request DMA or bus master access. These
signals are typically connected to external Super I/O device. An
internal pull-up resistor is provided on these signals.
LDRQ1# may optionally be used as GPIO.
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