8224 N/B Maintenance
8224 N/B Maintenance
88
5.1 Intel 945G/945P North Bridge (5)
Clock, Reset, and Miscellaneous
Signal Name
Type
Description
HCLKP
HCLKN
I
HCSL
Differential Host Clock In:
These pins receive a differential host clock from the external clock
synthesizer. This clock is used by all of the (G)MCH logic
that is in the Host clock domain. Memory domain clocks are also
derived from this source.
GCLKP
GCLKN
I
HCSL
Differential PCI Express* Clock In:
These pins receive a differential 100 MHz Serial Reference clock
from the external clock synthesizer. This clock is used to generate the
clocks necessary for the support of PCI Express.
DREFCLKN
DREFCLKP
I
HCSL
Display PLL Differential Clock In
RSTIN#
I
HVIN
Reset In:
When asserted, this signal will asynchronously reset the (G)MCH
logic. This signal is connected to the PCIRST# output of the Intel
®
ICH7. All PCI Express graphics attach output signals will also
tri-state compliant to
PCI Express* Specification, Revision 1.0a
.
This input should have a Schmitt trigger to avoid spurious resets.
This signal is required to be 3.3 V tolerant.
PWROK
I
HVIN
Power OK:
When asserted, PWROK is an indication to the (G)MCH that core
power has been stable for at least 10 us.
EXTTS#
I
CMOS
External Thermal Sensor Input:
This signal may connect to a precision thermal sensor located on or
near the DIMMs. If the system temperature reaches a dangerously
high value, then this signal can be used to trigger the start of system
thermal management. This signal is activated when an increase in
temperature causes a voltage to cross some threshold in the sensor.
EXP_EN
I
CMOS
PCI Express SDVO Concurrent Select:
0 = Only SDVO or PCI Express operational
1 = SDVO and PCI Express operating simultaneously via PCI
Express port
NOTES:
For the 82945P MCH, this signal should be pulled low.
EXP_SLR
I
CMOS
PCI Express* Lane Reversal/Form Factor Selection:
(G)MCH’s PCI Express lane numbers are reversed to differentiate
Balanced Technology Extended (BTX) or ATX form factors.
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX
Platforms)
1 = Normal operation (ATX Platforms)
ICH_SYNC# O
HVCMOS
ICH Sync:
This signal is connected to the MCH_SYNCH# signal on the ICH7.
DDR2 DRAM Reference and Compensation
Signal Name
Type
Description
SRCOMP[1:0]
I/O
System Memory RCOMP
SOCOMP[1:0]
I/O
A
DDR2 On-Die DRAM Over Current Detection (OCD) Driver
Compensation
SMVREF[1:0]
I
A
SDRAM Reference Voltage:
These signals are reference voltage inputs for each SDQ_x, SDM_x,
SDQS_x, and SDQS_x# input signals.
Direct Media Interface (DMI)
Signal Name
Type
Description
DMI_RXP[3:0]
DMI_RXN[3:0]
I/O
DMI
Direct Media Interface:
These signals are receive differential pairs (Rx).
DMI_TXP[3:0]
DMI_TXN[3:0]
O
DMI
Direct Media Interface:
These signals are transmit differential pairs (Tx).
Clock, Reset, and Miscellaneous (Continued)
Signal Name
Type
Description
XORTEST I/O
GTL+
XOR Test:
This signal is used for Bed of Nails testing by OEMs to execute XOR
Chain test.
LLLZTEST I/O
GTL+
All Z Test:
As an input this signal is used for Bed of Nails testing by OEMs to
execute XOR Chain test. It is used as an output for XOR chain
testing.
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