8224 N/B Maintenance
8224 N/B Maintenance
97
5.2 Intel ICH7-M South Bridge (8)
General Purpose I/O Signals
Name
Type Tolerance Power
Well Description
GPIO49
I/O
V_CPU_IO
V_CPU_IO
Multiplexed with CPUPWRGD
GPIO48
I/O
3.3 V
Core
Multiplexed with GNT4#
GPIO[47:40]
N/A
3.3 V
N/A
Not implemented.
GPIO[39:38]
I/O
3.3 V
Core
Unmultiplexed.
GPIO37
I/O
3.3 V
Core
Multiplexed with SATA3GP.
GPIO36
I/O
3.3 V
Core
Multiplexed with SATA2GP.
GPIO35
I/O
3.3 V
Core
Multiplexed with SATACLKREQ#.
GPIO34
I/O
3.3 V
Core
Unmultiplexed.
GPIO33
I/O
3.3 V
Core
Unmultiplexed.
GPIO32
I/O
3.3 V
Core
Unmultiplexed.
GPIO31
I/O
3.3 V
Resume
Multiplexed with OC7#
GPIO30
I/O
3.3 V
Resume
Multiplexed with OC6#
GPIO29
I/O
3.3 V
Resume
Multiplexed with OC5#
GPIO28
I/O
3.3 V
Resume
Unmultiplexed.
GPIO27
I/O
3.3 V
Resume
Unmultiplexed.
GPIO26
I/O
3.3 V
Resume
Unmultiplexed.
GPIO25
I/O
3.3 V
Resume
Unmultiplexed.
GPIO24
I/O
3.3 V
Resume
Unmultiplexed. Not cleared by CF9h reset
event.
GPIO23
I/O
3.3 V
Core
Multiplexed with LDRQ1#
GPIO22
I/O
3.3 V
Core
Multiplexed with REQ4#
GPIO21
I/O
3.3 V
Core
Multiplexed with SATA0GP.
GPIO20
I/O
3.3 V
Core
Unmultiplexed.
GPIO19
I/O
3.3 V
Core
Multiplexed with SATA1GP.
GPIO18
I/O
3.3 V
Core
Unmultiplexed.
GPIO17
I/O
3.3 V
Core
Multiplexed with GNT5#.
GPIO16
I/O
3.3 V
Core
Unmultiplexed.
GPIO[15:12]
I/O
3.3 V
Resume
Unmultiplexed.
GPIO11
I/O
3.3 V
Resume
Multiplexed with SMBALERT#
GPIO[10:8]
I/O
3.3 V
Resume
Unmultiplexed.
GPIO[7:6]
I/O
3.3 V
Core
Unmultiplexed.
GPIO[5:2]
I/OD
5 V
Core
Multiplexed with PIRQ[H:E]#.
General Purpose I/O Signals (Continued)
Name
Type Tolerance Power Well Description
GPIO1
I/O
5 V
Core
Multiplexed with REQ5#.
GPIO0
I/O
3.3 V
Core
Unmultiplexed.
NOTES:
1. GPI[15:0] can be configured to cause a SMI# or SCI. Note that a GPI can be routed to either an
SMI# or an SCI, but not both.
2. Some GPIOs exist in the VccSus3_3 power plane. Care must be taken to make sure GPIO signals
are not driven high into powered-down planes. Some ICH7 GPIOs may be connected to pins on
devices that exist in the core well. If these GPIOs are outputs, there is a danger that a loss of core
power (PWROK low) or a Power Button Override event will result in the Intel ICH7 driving a pin
to a logic 1 to another device that is powered down..
PCI Express* Signals
Name Type
Description
PETp[1:4],
PETn[1:4]
O
PCI Express* Differential Transmit Pair 1:4
PERp[1:4],
PERn[1:4]
I
PCI Express Differential Receive Pair 1:4
PETp[5:6],
PETn[5:6]
(Intel® ICH7R
Only)
O
PCI Express* Differential Transmit Pair 5:6
Reserved: ICH7
PERp[1:4],
PERn[5:6]
(ICH7R Only)
I
PCI Express Differential Receive Pair 5:6
Reserved: ICH7
SM Bus Interface Signals
Name Type
Description
SMBDATA
I/OD
SMBus Data:
External pull-up resistor is required.
SMBCLK
I/OD
SMBus Clock:
External pull-up resistor is required.
SMBALERT
#/
GPIO11
I
SMBus Alert:
This signal is used to wake the system or generate SMI#. If not used
for SMBALERT#, it can be used as a GPIO.
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