8224 N/B Maintenance
8224 N/B Maintenance
14
•
Raw bit-rate on the data pins of 2.5Gb/s, resulting in a real bandwidth per pair of 250 MB/s given the 8/10
encoding used to transmit data across this interface
•
Maximum theoretical realized bandwidth on interface of 4 GB/s in each direction simultaneously, for an
aggregate of 8 GB/s when x16
•
100 MHz differential reference clock (shared by PCI Express Gfx and DMI)
•
STP-AGP/AGP_BUSY Protocol equivalent for PCI Express based attach is via credit based PCI Express
mecanism
•
PCI Express power management support: L0s, L1, L2/L3 Ready, L3
•
Lane# 0 only for signaling and detection of exit from L0s and L1
•
Hierarchical PCI-compliant configuration mechanism for downstream devices (i.e., normal PCI 2.2
Configuration space as a PCI-to-PCI Bridge)
•
PCI Express Extended Configuration Space. The first 256 bytes of configuration space aliases directly to the
PCI Compatibility configuration space. The remaining portion of the fixed 4KB block of memory-mapped
space above that (starting at 100h) is known as extended configuration space
•
PCI Express Enhanced Addressing Mechanism. Accessing the device configuration space in a flat memory
mapped fashion
•
Automatic discovery, negotiation, and training of link out of reset
•
Supports traditional PCI style traffic (asynchronous snooped, PCI ordering)
•
Supports traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering)
•
Support for peer segment destination write traffic (no peer-to-peer read traffic) in Virtual Channel 0 only
MiTac Secret
Confidential Document
