Mesa 7I43, Руководство пользователя

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7I43 15
OPERATION
EPP-FPGA INTERFACE
The EPP interface implements a simple multiplexed 8 bit data/address bus. The
EPPIOPR8 configuration can be used as an example of an EPP interface in the FPGA.
This is a simple GPIO interface organized as six eight bit ports.
USB-FPGA INTERFACE
The USB interface differs between the 7I43 and 7I43H. The 7I43 uses a FTDI USB
interface chip, the FT245R. This is a Full speed interface chip (12 Mbps max). The
FT245R appears as a single endpoint communication device, basically a simple
bidirectional byte-stream with receive and transmit FIFOs. In order to use the USB
configuration and interface you must load the appropriate drivers for you operating system.
These drivers are available at FTDICHIP.COM. The utilities supplied with the 7I43 utilize
the VCP (Virtual COM Port) series drivers.
The 7I43H uses a FT2232H high speed USB interface chip (480 Mbps). Unlike the
FT245R used in the 7I43, the FT2232H appears as two serial ports. Only the first port is
used by the 7I43H. The supplied configurations support the same FIFO interface mode as
the 7I43 and the same pinout, but the 7I43H also has the FPGA connections to support
the high speed synchronous mode that allows host transfer rates up to 25M bytes per
second. The default mode is limited to 10 M bytes per second.
The FPGA interface uses a bidirectional 8 bit data bus that is shared with the EPP
interface on the 7I43). Because of this sharing you cannot operate the USB and EPP
interfaces simultaneously.
SIGNAL NAME FPGA PIN DIRECTION FUNCTION
USBWRITE 56 FROM FPGA XMIT DATA STROBE
/USBRD 55 FROM FPGA RECV DATA STROBE
/USBTXE 83 TO FPGA XMIT FIFO NOT FULL
/USBRXF 69 TO FPGA RECV FIFO HAS DATA
D0 68 BIDIR DATA BUS
D1 63 BIDIR DATA BUS
D2 60 BIDIR DATA BUS
D3 59 BIDIR DATA BUS