Mesa 7I43, Руководство пользователя

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7I43 14
OPERATION
CLOCK SIGNALS
The 7I43 has a 50 MHz crystal controlled clock signal routed to pin 53 (GCLK3) on
the FPGA. Four user I/O pins are also GCLK pins:
IO BIT GCLK FPGA PIN IO BIT GCLK FPGA PIN
IOBIT0 GCLK6 127 IOBIT24 GCLK7 128
IOBIT17 GCLK4 124 IOBIT40 GCLK5 125
EPP-FPGA INTERFACE
The interface from host EPP printer port to the FPGA uses 12 FPGA pins. These
consist of an eight bit bidirectional data bus (D0..D7), and four handshake lines. Note that
the handshake lines are fed through the CPLD so depend on the standard CPLD
configuration. The D bus connects to the FPGA through 100 Ohm resistors. These
resistors provide 5V tolerance and series line termination for driving the cable.
P2 PIN EPPNAME SPPNAME FPGA PIN DIRECTION
1 /WRITE /STROBE 84 TO FPGA
2 /DSTROBE /AUTOFD 79 TO FPGA
8 /ASTROBE /SELECTIN 80 TO FPGA
21 WAIT BUSY 82 FROM FPGA
3 D0 D0 68 BIDIR
5 D1 D1 63 BIDIR
7 D2 D2 60 BIDIR
9 D3 D3 59 BIDIR
11 D4 D4 51 BIDIR
13 D5 D5 50 BIDIR
15 D6 D6 47 BIDIR
17 D7 D7 46 BIDIR