35
Magtrol Model 6530 Three-Phase Power Analyzer
Chapter 4 – Operating Principles
THEOR
Y
Magtrol 7500 Series Power Analyzer
4.1.3
e
xternaL
s
hunt
The external shunt signal is brought in through a precision voltage divider of 9.1 k and 9.1 k resistors.
The gain is 0.50. This signal is buffered and passed into a programmable gain section. The gains
for the voltage ranges are given below.
range
resistors
gain ( amplifier )
50 mV
12 k / 620
-19.350
250 mV
2.4 k / 620
-3.871
500 mV
1.2 k / 620
-1.936
1000 mV
620 / 620
-1.000
The signal is then presented to an AD7722AS 16-bit analog to digital converter. The part accepts
an input signal of +/- 1.25 volts centered on a 2.5 VDC volt bias. The chart below shows system
input at 10% and 100% of range.
range
volts in (vdC)
gain (total)
volts at a/d input
bits
50 mV
0.005
-9.67500
-0.0484
1268
0.050
-9.67500
-0.4838
12681
250 mV
0.025
-1.93550
-0.0484
1268
0.250
-1.93550
-0.4839
12684
500 mV
0.050
-0.96800
-0.0484
1269
0.500
-0.96800
-0.4840
12688
1000 mV
0.100
-0.50000
-0.0500
1311
1.000
-0.50000
-0.5000
13107
Converter Resolution: 2.5 / 2^16 = 2.5 / 65536 = 0.00003814697
4.2
digital proCessing
Starting at the AD7722AS analog to digital converter, the input clock to the device is 14.31818
Mhz. This clock frequency gives a sample rate or data output rate of 14318180 / 64 = 223721.5625
samples per second.
The 7500 Power Analyzer uses FPGA technique to implement DSP computing and IIR filter. The
data can be stored up to 64 bit.
