61
2.20
SXR, SXT and CGEN BIST Configuration Memory
The block diagram of the BIST module for SXR, SXT and CGEN is shown in Figure 24. The
table in this chapter describes control registers of BIST module.
There is one test vector generator which supplies the test vectors for CGEN, SXT and
SXR modules.
The register BSTART at 0x00A8[0] is used to initiate the BIST procedure for the
selected modules. Registers BENC, BENR and BENT indicates which modules are to be
tested. As an example, , if BENC=1, BENR=0 and BENT=0 when BIST start is initiated, then
the test procedure will be performed on SXR only. If BENC=1, BENR=1 and BENT=1 when
BIST start is initiated, then BIST will be performed for CGEN, SXR and SXT.
When BSTATE indicates the end of the BIST procedure, BSIGT, BSIGR and BSIGC
registers will contain BIST signatures.
Table 21: BIST configuration memory
Address (15 bits)
Bits
Description
0x00A8
15 – 9
8
7
6
5
4
3
2
1
0
BSIGT[6:0]: BIST signature, Transmitter, LSB.
Default: 0
BSTATE: BIST state indicator
(read only)
0 – BIST is not running
(default)
1 – BIST in progress
Reserved
EN_SDM_TSTO_SXT: Enables the SDM_TSTO<12:0> outputs which will buffer the
SDM outputs (inputs to the frequency divider) for testing purposes.
0 – all outputs are grounded
(default)
1 – SDM_TSTO active
EN_SDM_TSTO_SXR: Enables the SDM_TSTO<12:0> outputs which will buffer the
SDM outputs (inputs to the frequency divider) for testing purposes.
0 – all outputs are grounded
(default)
1 – SDM_TSTO active
EN_SDM_TSTO_CGEN: Enables the SDM_TSTO<12:0> outputs which will buffer
the SDM outputs (inputs to the frequency divider) for testing purposes.
0 – all outputs are grounded
(default)
1 – SDM_TSTO active
BENC: enables CGEN BIST
0 – disabled
(default)
1 – enabled
BENR: enables receiver BIST
0 – disabled
(default)
1 – enabled
BENT: enables transmitter BIST
0 – disabled
(default)
1 – enabled
BSTART: Starts delta sigma built in self test. Keep it at 1 one at least three clock
cycles.
0 –
(default)
0-to-1 – positive edge activates BIST
Default
: 00000000 00000000
0x00A9
15 – 0
BSIGT[22:7]: BIST signature, Transmitter, MSB
(read only)
Default
: 00000000 00000000
0x00AA
15 – 0
BSIGR[15:0]: BIST signature, Receiver, LSB
(read only)
Default
: 00000000 00000000
0x00AB
15 – 7
6 – 0
BSIGC[8:0]: BIST signature, CGEN , LSB
(read only)
BSIGR[22:16]: BIST signature, Receiver, MSB
(read only)
Default
: 00000000 00000000
0x00AC
15 – 14
13 – 0
Reserved
BSIGC[22:9]: BIST signature, CGEN , MSB
(read only)
Default
: 00000000 00000000
Содержание LMS7002M Series
Страница 2: ......
Страница 79: ...75 A Ap pp pe en nd di ix x 2 2 Control Block Diagrams ...