49
Address (15 bits)
Bits
Description
0x008C
15
14
13
12
11 – 8
7 – 4
3 – 0
COARSE_STEPDONE_CGEN:
Read only
COARSEPLL_COMPO_CGEN:
Read only
VCO_CMPHO_CGEN:
Read only
VCO_CMPLO_CGEN:
Read only
CP2_CGEN[3:0]: Controls the value of CP2 (cap from CP output to GND) in the PLL
filter.
Default: 6
cp2=CP2_PLL_SX*6*63.2fF
CP3_CGEN[3:0]: Controls the value of CP3 (cap from VCO Vtune input to GND) in
the PLL filter.
Default: 7
cp3=CP3_PLL_SX*248fF
CZ_CGEN[3:0]: Controls the value of CZ (Zero capacitor) in the PLL filter.
Default:
11
cz=CZ_PLL_SX*8*365fF
Default
: 00000110 01111011
0x008D
15 – 2
1 – 0
Reserved
RESRV_CGN[2:1]: Reserved
Default: 0
Default
: 00000000 00000000
Содержание LMS7002M Series
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Страница 79: ...75 A Ap pp pe en nd di ix x 2 2 Control Block Diagrams ...