94
A2.15
SXR, SXT and CGEN BIST Control Diagram
T
o
F
ee
db
ac
k
D
iv
id
er
s
CGEN
SXT
SXR
Signature
Generator
CGEN
Signature
Generator
SXT
Signature
Generator
SXR
BSIGC
0x00AC[13:0] &
0x00AB[15:7]
BSIGT
0x00A9[15:0] &
0x00A8[15:9]
BSIGR
0x00AB[6:0] &
0x00AA[15:0]
BIST FSM
BIST
Counter
BSTART
0x00A8[0]
BSTATE
0x00A8[8]
Test Vector
Generator
MUX
MUX
MUX
Control Signals
BENC
0x00A8[3]
BENR
0x00A8[2]
BENT
0x00A8[1]
FRAC_SDM_CGEN
0x0088[3:0] &
0x0087[15:0]
INT_SDM_CGEN
0x0088[13:4]
EN_SDM_TSTO_CGEN
0x0086[7]
EN_SDM_TSTO_SXT
0x011C[7] (MIMO B)
EN_SDM_TSTO_SXR
0x011C[7] (MIMO A)
FRAC_SDM_SXR
0x011E[3:0] &
0x011D[15:0]
INT_SDM_SXR
0x011E[13:4]
FRAC_SDM_SXT
0x011E[3:0] &
0x011D[15:0]
INT_SDM_SXT
0x011E[13:4]
Figure 24 SXR, SXT and CGEN BIST control structure
Содержание LMS7002M Series
Страница 2: ......
Страница 79: ...75 A Ap pp pe en nd di ix x 2 2 Control Block Diagrams ...