background image

 

Evaluating the ORCA ORSO42G5 with the

Lattice Semiconductor

High-Speed SERDES Board

 

12

2. Some newer test equipment provides adjustable bias voltage on the internal 50

 

 

 input terminations. This 

equipment may be directly connected to the SERDES Tx output, as shown below.

For this connection, the adjustable termination voltage should be set to the V

 

DDOB

 

 supply voltage used on the High-

Speed SERDES Board (1.5V, if internal supply is being used). This is the best means of observing the Tx data out-
put signals for DC coupled applications, since it eliminates any possible signal degradation caused by bias tee and
DC blocking elements.

 

References

 

Bias Tee Model 5575A, Picosecond Pulse Labs, Boulder CO, www.picosecond.com.

50

50

Evaluation Board

SERDES TX Output

V

DDOB

Vterm = 

V

DDOB

High Speed Equipment

with Adjustable Term

Input Voltage

Содержание ORCA ORSO42G5

Страница 1: ...umes the baseline board configuration listed below The user is also encouraged to experiment with other configurations All jumpers should be in their default position and default programming in the ispPAC POWR1208 as described in the Evaluation Board User Manual This will apply power in the recommended sequence and provide 3 3V VDDIO to all banks ispDOWNLOAD cable pDS4102 DL2 connected to the para...

Страница 2: ...p back ORSO4_FELB6 Bitstream The orso4_felb6 bit design has been created as a base for all the described evaluation setups for the ORSO42G5 device As shown in Figure 3 the design takes advantage of the four SERDES channels available on the board The orso4_felb6 bitstream and the ORCAstra macros used in the tests are included in the package downloaded from www latticesemi com products devtools hard...

Страница 3: ...servation and measurement of the data eye generated by the device The ORSO42G5 device s major mode will produce a SONET scrambled data eye The same experimental setup can be used for near end loop back tests Other data pattern eye diagrams can be measured using far end loop back setups discussed later in this docu ment In this example either channel AC or AD can be used to evaluate a SONET scrambl...

Страница 4: ...ansmit Eye Diagram Setup Transmit Eye Diagram Test Procedures SONET Scrambled Data Eye 1 Connect the system as shown in Figure 4 The scope SMA cables should be connected to the HDOUTP_Bx and HDOUTN_Bx SMA connectors on the board 2 Power up the system 3 Start the clock generator and provide a nominal 155 52MHz CML reference clock 4 Download the orso4_felb6 bit bitstream into the ORSO42G5 5 Run the ...

Страница 5: ... 3 Far end Loop back For a Far End Loop back FELB test using the ORSO42G5 device the reference clock for the ORSO42G5 and for the data source must be frequency locked This is a mandatory requirement since the ORSO42G5 transmitter always uses the local reference clock Three types of FELB can be performed with the ORSO42G5 device Each type uses a different data path for the transmit and receive bloc...

Страница 6: ...tion 0xF6F6F6F628282828 SONET framing is established and the data is optionally descrambled After framing is established the aligned 32 bit data is transmitted to the FPGA along with a frame pulse DOUTBx_FP to indicate the start of the SONET frame The orso4_felb6 bit design uses an asynchronous FIFO to cross clock domains to the local reference clock REFCLK The data is then sent back into the embe...

Страница 7: ...he data back to the transmit interface to the embedded ASIC core as 32 bit data and frame pulse DINBx_FP for each channel Inside the Tx SONET block TOH bytes are optionally inserted and the 32 bit data is optionally re scrambled The data is then sent through the MUX block converted back to 8 bits serialized and transmitted via the CML buffer Setup Requirements Far End Loop back Testing You will ne...

Страница 8: ...ing the ORCAstra application SONET FELB 1 Connect the system as shown in Figure 8 The data SMA cables should be connected to the HDIN_Bx and HDOUTN_Bx SMA connectors on the board 2 Power up the system 3 Start the clock generator to provide a nominal 155 52MHz CML reference clock 4 Download the orso4_felb6 bit bitstream into the ORSO42G5 5 Run the sonet_felb fpm macro using the pull down menu in th...

Страница 9: ...lication can be used to control this selection When AUTO_TOH mode is enabled the Tx SONET block inserts all of the TOH bytes in the SONET frame This mode overwrites any default TOH values If AUTO_TOH mode is used the SONET scrambler descrambler must also be used An AUTO_SOH mode can also be selected using the ORCAstra application In this mode A1 A2 and or B1 bits are optionally inserted by the cor...

Страница 10: ...minated to ground they do not provide the required termination bias voltage When this equip ment is directly connected to the SERDES output it will provide an incorrect DC bias and prevents proper output buffer operation Inserting the bias tee module in the SERDES output connection to the oscilloscope allows the application of the required dc bias condition and provides the dc voltage translation ...

Страница 11: ...cy ranges and DC cur rent levels from several different vendors Lattice uses a Picosecond Pulse Lab bias tee More detailed character ization and application documents are available from this vendor See the References section at the end of this document Q Can the SERDES output be observed without a bias tee module Yes in two different ways as shown below 1 For AC coupled SERDES interface applicatio...

Страница 12: ...on voltage should be set to the VDDOB supply voltage used on the High Speed SERDES Board 1 5V if internal supply is being used This is the best means of observing the Tx data out put signals for DC coupled applications since it eliminates any possible signal degradation caused by bias tee and DC blocking elements References Bias Tee Model 5575A Picosecond Pulse Labs Boulder CO www picosecond com 5...

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