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tn1070_01
Evaluating the ORCA ORSO42G5 with the
High-Speed SERDES Board
April 2004
Technical Note TN1070
Introduction
Contained in this package is information that will assist you in evaluating and verifying your ORCA
®
ORSO42G5
designs using the Lattice High-Speed SERDES Board and the ORCAstra system bus control panel (available for
download from the Lattice web site at www.latticesemi.com/products/devtools/software/orcastra/index.cfm).
The Lattice High-Speed SERDES Board supports a number of testing and evaluation setups for both the
ORT42G5 and the ORSO42G5. This document will cover some common types of evaluation testing that can be
performed on the ORSO42G5 device in SERDES-only and SONET modes. The tests include transmitter eye dia-
gram measurement, SONET Near-end Loop-back and SERDES-only, SONET and Aligned SONET Far-end Loop-
back. All of the described evaluation setups use the orso4_felb6.bit bitstream. This bitstream is included with the
package you have downloaded from the Lattice web site at www.latticesemi.com/products/devtools/hard-
ware/orso42g5-board/index.cfm. A unique ORCAstra macro is used to configure the device for each test.
PC and Evaluation Board Setup
This document assumes the ORCAstra application and bitstream programming software (ispVM
®
) are installed on
the user’s PC. It also assumes the baseline board configuration listed below. (The user is also encouraged to
experiment with other configurations.)
• All jumpers should be in their default position and default programming in the ispPAC
®
-POWR1208 as
described in the Evaluation Board User Manual. This will apply power in the recommended sequence and
provide 3.3V V
DDIO
to all banks.
• ispDOWNLOAD
®
cable (pDS4102-DL2) connected to the parallel port of the PC and to the ispVM connec-
tor on the board (J30). The pDS4102-DL2 is included with the Lattice High-Speed SERDES Board. Alter-
nately, a HW-USB-1A ispDOWNLOAD cable can be used.)
• ORCAstra connected to the parallel or USB port on the PC and the ORCAstra Interface DB-25 or USB con-
nector on the board (J108).
• External differential clock connected to the External System Clock SMA connectors (J87/J88 and J84/J85).
• External power should be provided from the Molex cable and power module.
Recommended Reading
• ORSO42G5 Data Sheet
• ORCA Series 4 FPGA Data Sheet
• ispVM System Software Data Sheet
• ispDOWNLOAD Cable Data Sheet
• High-Speed SERDES Briefcase Board User Manual
• ORCAstra System Bus Control Panel User Manual
Loop-back Description
Two types of high-speed loop-back are discussed in this document: Near-End Loop-back and Far-End Loop-back.
Near-End Loop-back (NELB) is defined as the data path from the FPGA Transmit into the SERDES and back
through the SERDES to the FPGA Receive as shown in Figure 1. The actual loop-back connection is made inter-
nally at the interfaces to the transmit and receive CML buffers of the ORSO42G5 device.
