Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor
High-Speed SERDES Board
5
Now that the eye is present, the system can be manipulated to improve and/or distort the eye diagram. The
ORCAstra software can be used to change the pre-emphasis settings for the CML output buffer, change the half-
amplitude setting for the CML output buffer, change the half-rate setting for the Tx SERDES channel, or change the
frequency of the incoming reference clock. The Tx SERDES channel can also be powered down using the ORCA-
stra application.
Note: To obtain a valid eye diagram measurement, both outputs of the CML buffer must be connected to the same
load. A difference in the loading of the P and the N outputs of the CML buffer will degrade the measured data eye.
Near-end Loop-back
The same setup can also be used for high speed Near-End Loop-back (NELB) testing. Once the data eye is
present, the AC or AD channel can be placed in NELB by setting the LOOPEN bit with the ORCAstra GUI. Select-
ing the LOOPEN bit will also disable the CML output buffer, so the eye diagram will disappear on the scope. The
user can now use the ORCAstra control panel to manipulate all of the Tx features in the ORSO42G5 in SONET
mode, such as insertion of B1, AIS and RDI. The Rx SONET error-detection block circuitry is also functional, and
can be observed either using ORCAstra, or for channel AC, at the FPGA output pins shown in Figure 3.
Far-end Loop-back
For a Far-End Loop-back (FELB) test using the ORSO42G5 device, the reference clock for the ORSO42G5 and for
the data source must be frequency locked. This is a mandatory requirement since the ORSO42G5 transmitter
always uses the local reference clock.
Three types of FELB can be performed with the ORSO42G5 device. Each type uses a different data path for the
transmit and receive blocks of the embedded ASIC core. The three paths are SERDES-Only, SONET and Aligned
SONET.
SERDES-only Tests
The active blocks in the SERDES-only data path are shown in Figure 5. Serial data is input through the CML buffer
into the SERDES. Clock and data recovery is then performed, producing an 8-bit data bus and recovered clock. A
MUX block then converts the 8-bit data to 32-bit data. This 32-bit data is transmitted into the FPGA. The
orso4_felb6.bit design uses an asynchronous FIFO to cross clock domains to the local reference clock (REFCLK).
The 32-bit data is then sent back into the embedded ASIC core, then through the MUX block to convert back to 8
bits. Finally, it is re-serialized and transmitted via the CML buffer.
Figure 5. SERDES-only Data Path (orso4_felb6.bit, Channel BC or BD)
The SERDES-only data path can be used to evaluate any type of data pattern. The data pattern must be guaran-
teed to provide an adequate density of 1’s for the ORSO42G5 SERDES run length. For example, a Pseudo-Ran-
dom Bit Stream (PRBS) test can be performed using an external data source and checker and various types of
HDIN_Bx
HDOUT_Bx
Rx SERDES
Tx SERDES
RWCKBx
ASIC
FPGA
TSYSCLKBx
TCK78B (Derived from REFCLK)
FIFO
32-bit
Data
