Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor
High-Speed SERDES Board
6
PRBS 2
n
-1 sequences to test the ORSO42G5 device. Different types of transmit data eyes can also be observed
and measured using different data patterns in this mode.
SONET Tests
The active blocks in the SONET data path are shown in Figure 6. The SONET data path requires SONET data to
be sent from an external data source to the Rx input. The Tx output then sends the data back to the data source for
checking.
Figure 6. SONET Data Path (orso4_felb6.bit, Channel BC or BD)
Serial data is input through the CML buffer into the SERDES. Clock and data recovery is then performed, produc-
ing an 8-bit data bus and recovered clock. A MUX block then converts the 8-bit data to 32-bit data. This 32-bit data
is then sent to the Rx SONET block. Inside the Rx SONET block the data is aligned to the A1/A2 transition
(0xF6F6F6F628282828), SONET framing is established, and the data is optionally descrambled.
After framing is established, the aligned 32-bit data is transmitted to the FPGA along with a frame pulse
(DOUTBx_FP) to indicate the start of the SONET frame. The orso4_felb6.bit design uses an asynchronous FIFO to
cross clock domains to the local reference clock (REFCLK). The data is then sent back into the embedded core as
32 bits of data and a frame pulse (DINBx_FP). Inside the Tx SONET block, TOH bytes are optionally inserted, and
the 32-bit data is optionally re-scrambled. The data is then sent through the MUX block, converted back to 8 bits,
serialized and transmitted via the CML buffer.
Aligned SONET Tests
The active blocks in the aligned SONET data path are shown in Figure 7. The aligned SONET data path requires
SONET data to be sent from an external data source to the Rx input. The Tx output sends the data back to the data
source for checking.
HDIN_Bx
HDOUT_Bx
Rx SERDES
Tx SERDES
Rx SONET
Tx SONET
RWCKBx
ASIC
FPGA
TSYSCLKBx
TCK78B (Derived from REFCLK)
FIFO
32-Bit Data
DOUTBx_FP
