Evaluating the ORCA ORSO42G5 with the
Lattice Semiconductor
High-Speed SERDES Board
7
Figure 7. Aligned SONET Data Path (orso4_felb6.bit, Channel AC and AD)
Serial data is input through the CML buffer into the SERDES. Clock and data recovery is then performed, produc-
ing an 8-bit data bus and recovered clock. A MUX block then converts the 8-bit data to 32-bit data. This 32-bit data
is then sent to the Rx SONET block. Inside the Rx SONET block the data is aligned to the A1/A2 transition
(0xF6F6F6F628282828), SONET framing is established, and the data is optionally descrambled.
After framing is established, the aligned 32-bit data is transmitted to the alignment FIFO. The alignment FIFO
crosses clock domains from the recovered clock to the local reference clock (REFCLK), aligns the two channels
and sends the aligned data to the FPGA. The FPGA receives the 32-bit data along with aligned frame pulses
(DOUTAx_FP) to indicate the start of the SONET frame.
The orso4_felb6.bit design uses two registers to clock the data back to the transmit interface to the embedded
ASIC core as 32-bit data and frame pulse (DINBx_FP) for each channel. Inside the Tx SONET block TOH bytes are
optionally inserted and the 32-bit data is optionally re-scrambled. The data is then sent through the MUX block,
converted back to 8 bits, serialized and transmitted via the CML buffer.
Setup Requirements: Far-End Loop-back Testing
You will need the following to complete this evaluation:
• ORSO42G5 High-Speed SERDES Board configured as described earlier
• Orso4_felb6.bit bitstream and bitstream programming devices (ispDOWNLOAD cable and ispVM running
on a PC).
• 5V DC wall power supply.
• Clock source capable of driving a CML input clock (77.76-155.52MHz) and SMA cables from the clock
source to the Lattice High-Speed SERDES Board.
• ORCAstra GUI application and serdes_only_felp.fpm and sonet_felp.fpm macros.
• Data source with SONET capability and frequency locked to the ORSO42G5 reference clock. Typically this
data source will also perform checks on the received data stream.
A typical test setup is shown in Figure 8.
HDIN_A
HDOUT_Ax
Rx SERDES
Tx SERDES
Rx SONET
FIFO
Tx SONET
RWCKAx
ASIC
FPGA
TSYSCLKAx
TCK78A (Derived from REFCLK)
32-Bit Data
DOUTAx_FP
