3
LatticeXP2 Advanced
Lattice Semiconductor
Evaluation Board User’s Guide
• Prototyping areas with access to 14 I/O pins
• Selectable I/O bank voltages
• Four pairs of SMA connectors for high speed differential signals
• Oscillator socket for both half-size and full-size oscillators
• 3.3V, 2.5V, 1.8V, 1.2V and ADJ (adjustable voltage) powers generated from a single 5V to 28V power source
• ispPAC
®
-POWR1220AT8 Power Manager II device for monitoring the 3.3V, 2.5V, 1.8V, 1.2V, ADJ voltages and
DDR Vref, Vtt voltages
• ispVM
®
System programming support
General Description
The heart of the board is the LatticeXP2 non-volatile FPGA. The board also provides several different interconnec-
tions and support devices that permit it to be used for a variety of purposes. The PCI connector, DDR2 socket, and
Tri-speed Ethernet PHY are useful for applications using Lattice IP cores.
A number of connectors are useful for general purpose of the LatticeXP2 I/O capability. These include the SMA
connectors, RS-232, Video Tx/Rx MDR connectors, and the various generic prototype access points.
The CompactFlash connector is also useful for expansion purposes. It provides the ability to add storage, or com-
munication capabilities to the board.
Other features on the board help in evaluating the capabilities and performance of the LatticeXP2. The A/D, D/A,
and digital potentiometer are helpful for some basic mixed signal applications. The SMA connectors permit the
evaluation of high-speed differential signals, and protocols. The SPI memory showcases the failsafe capabilities of
the LatticeXP2.
The board also acts as a showcase for the ispPAC-POWR1220 power manager. The ispPAC-POWR1220 is a pro-
grammable device useful for safely managing the power supply system on the board. While the LatticeXP2 device
has no specific power-sequencing requirements, the ispPAC-POWR1220 device can be used to sequence and
monitor voltages.
Additional Resources
Additional resources for the LatticeXP2 Advanced Evaluation Board, such as updates to this document, sample
programs and links to demos can be found on the Lattice web site. Go to www.latticesemi.com/boards, and navi-
gate to the appropriate page for this board.
Initial Setup and Handling
The following is recommended reading prior to removing the evaluation board from the static shielding bag and
may or may not apply to your particular use of the board.
CAUTION: The devices on the board can be damaged by improper handling.
The devices on the evaluation board contain fairly robust ESD (Electro Static Discharge) protection structures
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example
of ESD characterization requirements). Even so, the devices are static sensitive to conditions that exceed their
designed in protection. For example: higher static voltages, as well as lower voltages with lower series resistance
or larger capacitance than the respective ESD specifications require can potentially damage or degrade the
devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while han-
dling the evaluation board when it is removed from the static shielding bag. If you will not be using the board for a
