Lattice Semiconductor XP2 Advanced, Руководство пользователя

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LatticeXP2 Advanced
Lattice Semiconductor Evaluation Board User’s Guide
Seven Segment Display
The 7-segment LED located near the eight LEDs is controlled by LatticeXP2 Bank 4 I/O pins. The connections of
the segments are shown in Figure 3.
Figure 3. 7-Segment Display
LCD
The LCD module connector (J55) is a 2x9 header. This 18-pin header is compatible with quite a few character LCD
modules. Table 17 shows the pin function of the header and the connections to the bank 0 of the LatticeXP2 FPGA.
Table 17. LCD Header Connection
Pin # Function LatticeXP2 I/O Pin # Function LatticeXP2 I/O
1 Anode — 2 Cathode (GND) —
3 VSS(GND) — 4 VDD (5V) —
5 VO — 6 RS U14
7 R/W AA20 8 E AA21
9 DB0 AB20 10 DB1 AA22
11 DB2 V14 12 DB3 Y21
13 DB4 W14 14 DB5 Y22
15 DB6 U15 16 DB7 V15
17 Anode — 18 Cathode (GND) —
The VR4 potentiometer is used to limit the current that flows through the backlight LED on the LCD module. The
VR5 potentiometer is used to adjust the VO voltage that controls the LCD contrast.
When the following LCD modules are used, connect pin 1 to 16 to the backlight LCD module or connect pin 1 to 14
to the non-backlight LCD module:
Optrex:
• C-51505 Series: 20 characters x 2 lines
When the following LCD modules are used, connect pin 3 to 18 to the backlight LCD module or connect pin 3 to 16
to the non-backlight LCD module.