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LatticeXP2 Advanced

Lattice Semiconductor

Evaluation Board User’s Guide

USB 1.1

For implementing the USB interface, the LatticeXP2 board contains a USB 1.1 transceiver MAX3454EETE (or
NCN2500MNR2 from On Semiconductor), a type-A connector and a type-B USB connector. Note there is a third
USB connector, which is used for the built-in USB download cable, described later in this document.

Table 21. Header Settings for Configuring USB Interface as USB Host

Header/Connector

Jumper Position

Description

J21

Pin 1 and 2

Drive USB transceiver ENUM pin to GND to disconnect the internal 1.5K
resistor between Vtrm and D+ or D-.

J22 (D+)

Pin 1 and 2

Pull D+ signal low through an external 15K resistor.

J23 (D-)

Pin 1 and 2

Pull D- signal low through an external 15K resistor.

J24

Pin 1 and 2

Provide 5V power to the external USB device.

J16 (USB type A)

—

Type A is used while implementing USB host.

J20 (USB type B)

—

This connector is not used in this configuration.

Table 22. Header Settings for Configuring USB Interface as USB Device

Header/Connector

Jumper Position

Description

J21

Pin 2 and 3

Drive USB transceiver ENUM pin to 3.3V to connect the internal 1.5K
resistor between Vtrm and D+ or D-.

J22 (D+)

Pin 2 and 3

Disconnect D+ signal from the external 15K pull-down.

J23 (D-)

Pin 2 and 3

Disconnect D- signal from the external 15K pull-down.

J24

Pin 2 and 3

No 5V power is provided when implementing USB device.

J16 (USB type A)

—

This connector is not used in this configuration.

J20 (USB type B)

—

Type A is used while implementing USB host.

The connections between the USB 1.1 transceiver MAX3454EETE (or NCN2500MNR2 from On Semiconductor)
and the LatticeXP2 FPGA are shown in Table .

24

WP/IOIS16/IOCS16

D9

49

D10

D6

25

CD2

A9

50

GND

—

Table 23. Connections Between USB 1.1 Transceiver and LatticeXP2

Pin #

MAX3454EETE NCN2500MNR2

LatticeXP2 I/O

Description

1

SPD

DSPD

D4

Connect to LatticeXP2 bank 7 I/O

2

RCV

RCV

E3

Connect to LatticeXP2 bank 7 I/O

3

VP

VP

C1

Connect to LatticeXP2 bank 7 I/O

4

VM

VM

D1

Connect to LatticeXP2 bank 7 I/O

5

NC

EN_Vobus#

—

Connect to 3.3V

6

GND

GND

—

Connect to GND

7

SUS

SPND

E1

Connect to LatticeXP2 bank 7 I/O

8

NC

NC

—

No connect

9

OE#

OE#

D3

Connect to LatticeXP2 bank 7 I/O

10

D-

D-

—

Connect to USB connectors through 33 Ohm resistor

11

D+

D+

—

Connect to USB connectors through 33 Ohm resistor

12

Vtrm

Vreg

—

Connect to GND though a capacitor

Table 20. CompactFlash Connection (Continued)

Pin #

Function

LatticeXP2 I/O

Pin #

Function

LatticeXP2 I/O

«
...
13
14
15
16
17
...
»

Содержание XP2 Advanced

Страница 1: ...March 2011 Revision EB30_01 5 LatticeXP2 Advanced Evaluation Board User s Guide ...

Страница 2: ... LUT based logic distributed and embedded memory Phase Locked Loops PLLs pre engineered source synchronous I O and enhanced sysDSP blocks For a full description of the LatticeXP2 FPGA see the Lattice website for data sheets technical notes technology summaries and more www latticesemi com Some common uses for the LatticeXP2 Advanced Evaluation Board include Video and other DSP processing An analog...

Страница 3: ...safe capabilities of the LatticeXP2 The board also acts as a showcase for the ispPAC POWR1220 power manager The ispPAC POWR1220 is a pro grammable device useful for safely managing the power supply system on the board While the LatticeXP2 device has no specific power sequencing requirements the ispPAC POWR1220 device can be used to sequence and monitor voltages Additional Resources Additional reso...

Страница 4: ...n unplugging cables from the evaluation board the last connection unplugged should be the chassis GND connection to eval board GND If you have signal sources that are floating with respect to chassis GND attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation board If you are holding or carrying the board while it s not in a static shielding bag please...

Страница 5: ...cks at J53 VCC_IN and J51 GND The workbench power supply voltage has to be between 5 0V and 28 0V Table 1 Power Jack J54 Specifications Polarity Positive Center Inside Diameter 0 1 2 5mm Outside Diameter 0 218 5 5mm Current Capacity Up to 4A Power may also be supplied directly for each individual supply rail using banana jack connectors To enable this mode of operation the appropriate fuses must b...

Страница 6: ...he user to select the voltage VCCIO applied to each of the eight I O banks of the LatticeXP2 device Certain restrictions apply depending on which features of the board are being used Table 5 VCCIO Selection Jumper sysIO Bank Jumper Jumper on Pins 0 J34 1 3 VCC_3 3V 2 4 VCC_2 5V 3 5 VCC_1 8V 4 6 VCC_ADJ 6 J37 1 VCC_2 5V 2 VCC_1 8V 3 VCC_1 8V 4 VCC_3 3V 5 VCC_3 3V 7 VCC_3 3V Depending on the optiona...

Страница 7: ...CMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I II SSTL25 Class I II SSTL33 Class I II HSTL15 Class I HSTL18 Class I II SSTL18D Class I II SSTL25D Class I II SSTL33D Class I II HSTL15D Class I II HSTL18D Class I II PCI33 LVDS LVDS25E1 LVPECL1 BLVDS1 RSDS1 LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 SSTL18 Class I SSTL2 Class I II SSTL3 Class I II HSTL15 Class I HSTL18 Class I II SSTL18D Cl...

Страница 8: ...B ULC_GPLLC_IN_A J13 F7 Pair 1 P 0 PT5A ULC_GPLLT_FB_A J7 G7 Pair 1 N 0 PT5B ULC_GPLLC_FB_A J14 P4 Pair 2 P 6 PL37A J8 P5 Pair 2 N 6 PL37B J15 Y1 Pair 3 P 6 PL35A J9 AA1 Pair 3 N 6 PL35B 1 The SMA connector on J12 is shared with the on board oscillator When this SMA connector is used the jumper on J17 needs to be removed RJ 45 Connectors There are two RJ 45 connectors J5 and J43 on the evaluation ...

Страница 9: ...he JTAG connectors J25 J32 J39 and J40 are 1x10 headers The JTAG ports for the LatticeXP2 and ispPAC POWR1220AT8 devices can be configured as loop through connectors to allow for easy daisy chaining of multiple boards With proper jumper selection see the next section standard IDC ribbon cable can be used without the need to swap any wires on the cable The pinouts for these headers are provided in ...

Страница 10: ... not be used when the JTAG ports are chained together During chained programming the ispPAC POWR1220AT8 device will set the HVOUT1 signal pin 86 of U17 tri state until programming completes so the enable for the 3 3V power for the LatticeXP2 device will be interrupted during programming unless a jumper is installed at J52 After chained pro gramming of the ispPAC POWR1220AT8 the jumper at J52 can b...

Страница 11: ...Position POWR1220AT8 I O Pin Pin Name SW2 position 1 97 IN1 SW2 position 2 1 IN2 SW2 position 3 2 IN3 SW2 position 4 4 IN4 SW2 position 5 6 IN5 SW2 position 6 7 IN6 SW2 position 7 89 VPS0 SW2 position 8 90 VPS1 LEDs The eight user definable LEDs are provided on the lower right side of the board These LEDs are each wired to a separate general purpose I O as defined in the Table 15 The current limit...

Страница 12: ...P2 I O Pin Function LatticeXP2 I O 1 Anode 2 Cathode GND 3 VSS GND 4 VDD 5V 5 VO 6 RS U14 7 R W AA20 8 E AA21 9 DB0 AB20 10 DB1 AA22 11 DB2 V14 12 DB3 Y21 13 DB4 W14 14 DB5 Y22 15 DB6 U15 16 DB7 V15 17 Anode 18 Cathode GND The VR4 potentiometer is used to limit the current that flows through the backlight LED on the LCD module The VR5 potentiometer is used to adjust the VO voltage that controls th...

Страница 13: ...24 characters x 2 lines MDLS 40266 Series 40 characters x 2 lines Video TX and RX MDR Connectors The video TX J2 and RX J3 MDR connectors accept 7 1 LVDS 2 5v differential video signals The connections between the connector pins and LatticeXP2 I O are shown in Tables 18 and 19 All the pins are connected to Bank 6 I Os The Bank 6 supply voltage VCCIO_6 must be set to select 2 5V for proper LVDS 2 5...

Страница 14: ...n the connector pins and LatticeXP2 balls are shown in Table 20 All the pins are connected to Bank 1 I Os Table 20 CompactFlash Connection Pin Function LatticeXP2 I O Pin Function LatticeXP2 I O 1 GND 26 CD1 A8 2 D3 A14 27 D11 B8 3 D4 B13 28 D12 A7 4 D5 F12 29 D13 F9 5 D6 F11 30 D14 E9 6 D7 C12 31 D15 C8 7 CE1 CS0 E11 32 CE2 CS1 D8 8 A10 A13 33 VS1 B7 9 OE ATASEL B12 34 IORD B6 10 A9 A12 35 IOWR A...

Страница 15: ...o connect the internal 1 5K resistor between Vtrm and D or D J22 D Pin 2 and 3 Disconnect D signal from the external 15K pull down J23 D Pin 2 and 3 Disconnect D signal from the external 15K pull down J24 Pin 2 and 3 No 5V power is provided when implementing USB device J16 USB type A This connector is not used in this configuration J20 USB type B Type A is used while implementing USB host The conn...

Страница 16: ...me MAX3232 Pin LatticeXP2 I O LatticeXP2 Bank LatticeXP2 I O Type CTS 9 R2OUT C3 7 Input RXD 12 R1OUT B2 7 Input TXD 11 T1IN B1 7 Output RTS 10 T2IN C2 7 Output Connections Between MAX3232 and LatticeXP2 DDR2 The 200 pin SODIMM socket provides a built in 32 bit interface to standard 1 8V DDR2 SDRAM memory modules PC2 5300 Lattice recommends the Kingston KVR533D284 512 However other memories confor...

Страница 17: ...DDR2_DQ17 F22 2 45 DDR2_DQ18 J17 2 55 DDR2_DQ19 K17 2 57 DDR2_DQ20 K18 2 44 DDR2_DQ21 L17 2 46 DDR2_DQ22 H22 2 56 DDR2_DQ23 G22 2 58 DDR2_DM2 J16 2 52 DDR2_DQS2_P H21 2 51 DDR2_DQS2_N J21 2 49 DDR2_DQ24 H20 2 61 DDR2_DQ25 G20 2 63 DDR2_DQ26 E19 2 73 DDR2_DQ27 F19 2 75 DDR2_DQ28 J20 2 62 DDR2_DQ29 H19 2 64 DDR2_DQ30 C22 2 74 DDR2_DQ31 B22 2 76 DDR2_DM3 H17 2 67 DDR2_DQS3_P D22 2 70 DDR2_DQS3_N E22 ...

Страница 18: ... to the schematic and the National Semiconductor DP83865 Data Sheet for detailed information about the operation of the Ethernet PHY interface on this device Refer to Table 27 for a description of the Ethernet PHY con nections DDR2_A6 R16 3 94 DDR2_A7 T17 3 92 DDR2_A8 Y20 3 93 DDR2_A9 Y19 3 91 DDR2_A10 W22 3 105 DDR2_A11 G15 2 90 DDR2_A12 G16 2 89 DDR2_A13 F17 2 116 DDR_BA0 P20 3 107 DDR_BA1 P22 3...

Страница 19: ..._RX_D6 F13 1 ETH_RX_D7 G12 1 ETH_RX_DV C14 1 ETH_RX_ER E13 1 ETH_TX_CLK C15 1 ETH_TX_D0 D17 1 ETH_TX_D1 E18 1 ETH_TX_D2 C18 1 ETH_TX_D3 C19 1 ETH_TX_D4 A20 1 ETH_TX_D5 D19 1 ETH_TX_D6 D17 1 ETH_TX_D7 D18 1 ETH_TX_EN A19 1 ETH_TX_ER A21 1 PCI Connection The 124 pin PCI connector installed at the bottom left corner of the board is used for 32 bit PCI With this PCI con nector PCI IP and proper Lattic...

Страница 20: ... AD 27 I O PCI address and data bit 27 AB6 24 AD 25 I O PCI address and data bit 25 AA7 25 3 3V Vcc 3 3V voltage supply pin 3 3V 26 C BE 3 I O PCI bus command byte enable bit 3 Y8 27 AD 23 I O PCI address and data bit 23 W4 28 GND Vss System ground GND 29 AD 21 I O PCI address and data bit 21 W6 30 AD 19 I O PCI address and data bit 19 U8 31 3 3V Vcc 3 3V voltage supply pin 3 3V 32 AD 17 I O PCI a...

Страница 21: ...e supply pin 3 TMS I PCI JTAG TMS signal 4 TDI I JTAG TDI signal 5 5V Vcc 5V voltage supply pin 6 INTA O PCI INTA signal AB2 7 INTC O PCI INTC signal 8 5V Vcc 5V voltage supply pin 9 Reserved Reserved 10 VIO Vio VIO voltage supply pin 11 Reserved Reserved 14 3 3V AUX Vcca 3 3V auxiliary voltage supply 15 RST I PCI system reset AB3 16 VIO Vio VIO voltage supply pin 17 GNT I PCI arbitration grant AB...

Страница 22: ...7 GND Vss System ground GND 38 STOP I O PCI interface control STOP signal T11 39 3 3V Vcc 3 3V voltage supply pin 3 3V 40 Reserved Reserved 41 Reserved Reserved 42 GND Vss System ground GND 43 PAR I O PCI address and data PAR signal U10 44 AD 15 I O PCI address and data bit 15 U11 45 3 3V Vcc 3 3V voltage supply pin 3 3V 46 AD 13 I O PCI address and data bit 13 AB8 47 AD 11 I O PCI address and dat...

Страница 23: ...are shown in Table 31 Table 31 DAC Connections Description LatticeXP2 I O sysIO Bank RSTN K1 7 LOADREGN K2 7 LDACN J4 7 CSN M1 7 CLK M2 7 SDI L3 7 The AREF signal is used by both the ADC and DAC as the full scale voltage reference The AREF signal can be selected from three different sources a low drift band gap voltage provided at U2 the power supply voltage VCC_3 3v or an externally applied volta...

Страница 24: ...n exter nal download cable the jumper on J35 must be moved to shunt pins 1 and 2 This tri states the MachXO device preventing it from interfering with the external download cable Important Note The board must be un powered when connecting disconnecting or reconnecting the ispDOWN LOAD Cable or USB cable Always connect an ispDOWNLOAD Cable s GND pin black wire before connecting any other JTAG pins ...

Страница 25: ...to the black GND terminal J51 2 Check that the jumpers are installed as shown in Figure 4 Now move the J35 jumper from the left side two pins to be on the right side two pins 3 Connect the LatticeXP2 Evaluation Board to an external 5V supply 4 Push the SW1 USB Download reset button located just above the MachXO device U9 Connect a standard USB cable from your PC s USB connector to the USB download...

Страница 26: ...ialog 8 Select Browse and point to the location of the bitstream file Note that if you have a JED file output from isp LEVER you can convert it to a BIT file using ispVM and selecting the UFW Universal File Writer icon with the input file being the JED file from ispLEVER and the output file being a BIT file 9 Select Flash Device and in the Select Device window change the selections as shown in Fig...

Страница 27: ...10 Check that the SPI Serial Flash Device window now appears as shown in Figure 9 then press OK to close the SPI Serial Flash Device window Figure 9 SPI Serial Flash Device Dialog 11 Check that the Device Information window appears as shown in Figure 10 then press OK to close the Device Information window ...

Страница 28: ...left side until it reaches the right side of the win dow When downloading to SPI Flash is complete ispVM will then begin to verify the downloaded bitstream loaded into the SPI Flash with another small processing window and blue bar moving across it 14 Upon successful verification of the downloaded bitstream to SPI Flash the LatticeXP2 device can then be pro grammed by powering down the evaluation ...

Страница 29: ...ble connect to the 1x10 header by justifying the alignment to pin 1 VCC The board must be un powered when connecting disconnecting or reconnecting the ispDOWNLOAD Cable or USB cable Always connect an ispDOWNLOAD Cable s GND pin black wire before connecting any other JTAG pins Failure to follow these procedures can in result in damage to the LatticeXP2 FPGA and render the board inoperable 5 Start t...

Страница 30: ...the bitstream file Note that if you have a JED file output from isp LEVER you can convert it to a BIT file using ispVM and selecting the UFW Universal File Writer icon with the input file being the JED file from ispLEVER and the output file being a BIT file 9 Select Flash Device and in the Select Device window change the selections as shown in Figure 15 Press OK to close the Select Device window ...

Страница 31: ...10 Check that the SPI Serial Flash Device window now appears as shown in Figure 16 then press OK to close the SPI Serial Flash Device window Figure 16 SPI Serial Flash Device Dialog 11 Check that the Device Information window appears as shown in Figure 17 then press OK to close the Device Information window ...

Страница 32: ...left side until it reaches the right side of the win dow When downloading to SPI Flash is complete ispVM will then begin to verify the downloaded bitstream loaded into the SPI Flash with another small processing window and blue bar moving across it 14 Upon successful verification of the downloaded bitstream to SPI Flash the LatticeXP2 device can then be pro grammed by powering down the evaluation ...

Страница 33: ...d Evaluation Board User s Guide photo Updated Power Setup text section Updated USB Download text section May 2008 01 2 Corrected ball assignment for ETH_MDC in 10 100 1000 Ethernet PHY Connection Summary table January 2009 01 3 Updated ordering information January 2011 01 4 Updated the DDR2 text section March 2011 01 5 Added LatticeXP2 SRAM Configuration Using a Standard USB Cable at J33 and Latti...

Страница 34: ...Title Size Document Number Rev Date Sheet of B Lattice XP2 Advanced Engineering Board 484 fpBGA A 1 14 Bank 0 Bank 3 FPGA Bank 6 PCI 32 BIT Bank 5 Bank 7 Bank 1 Bank 2 Bank 4 Compact Flash PLL SMA I O Lattice Semiconductor Corporation Sheet 2 Bank 8 XP2 Sheet 10 Programming USB DL Sheets 4 9 Switches LEDs LCD Display Sheet 6 Power Sheet 12 13 FPGA Power Pins Sheet 5 DDR2 SDRAM 32 BIT Video I O Sig...

Страница 35: ... 10uF X7R C81 0 001uF 0402 C81 0 001uF 0402 1 2 C8 0 01uF C8 0 01uF D1 B320A Diodes Inc SMA_PKG D1 B320A Diodes Inc SMA_PKG R147 10K R147 10K R128 10K R128 10K VR1 50K POT Murata PV36Y503C01 PV37W VR1 50K POT Murata PV36Y503C01 PV37W 1 3 2 C3 0 1uF C3 0 1uF C63 0 1uF C63 0 1uF U2 LM385 SO U2 LM385 SO C73 0 001uF 0402 C73 0 001uF 0402 1 2 C85 0 1uF 0402 C85 0 1uF 0402 1 2 R7 100 R7 100 J15 SMA Conn...

Страница 36: ...3 1 2 3 R165 33 R165 33 C100 0 1uF 0402 C100 0 1uF 0402 R174 0 R174 0 C68 4 7uF Ceramic X5R 0603 C68 4 7uF Ceramic X5R 0603 1 2 R150 0 R150 0 R162 DNL R162 DNL R36 15K R36 15K R175 0 R175 0 R153 DNL R153 DNL 1 2 4 3 J20 USB Series B Receptacle Molex 67068 8000 1 2 4 3 J20 USB Series B Receptacle Molex 67068 8000 VBUS 1 D 2 D 3 GND 4 5 MH1 6 MH2 R177 0 R177 0 R160 DNL R160 DNL R35 15K R35 15K R79 0...

Страница 37: ...en TDI is selected ispPAC J49 CONFIGURATION 1 J49 short and J45 open default setting J39 for ispPAC programming only J40 for XP2 programming only CONFIGURATION 2 J49 open with J45 and J52 short J39 for programming both XP2 and ispPAC JTAG chained together J40 not used For chaining XP2 and ispPAC together 1 Remove the jumper on J49 and install it on J45 2 Connect the download cable to J39 TDI TCK T...

Страница 38: ... 10 48 M66EN 49 AD 08 52 AD 07 53 3 3V_54 54 AD 05 55 AD 03 56 Ground_57 57 AD 01 58 VIO_59 59 ACK64 60 5V_61 61 5V_62 62 C118 0 001uF 0402 C118 0 001uF 0402 R11 0 R11 0 C144 0 001uF 0402 C144 0 001uF 0402 1 2 C84 0 01uF 0402 C84 0 01uF 0402 1 2 C94 0 01uF 0402 C94 0 01uF 0402 C6 10uF Ceramic X5R 0805 C6 10uF Ceramic X5R 0805 J56 PCI EDGE CONN Solder Side J56 PCI EDGE CONN Solder Side TRST 1 12V 2...

Страница 39: ... oscillator clock output to the PLL clock input on the XP2 ball A2 Traces from the ECP2 to the CF connector must be less than 6 inches Ultra DMA is not supported Compact Flash Connector 12 8 SMA Connector AEP 9650 1113 005 P A2 N B3 Diff pair 50 ohm traces P F7 N G7 8 8 8 8 Place resistors next to FPGA arrange them to fit on 4 pads J6 SMA Connector J6 SMA Connector GND 2 GND 3 GND 4 GND 5 S 1 R56 ...

Страница 40: ...16 GND 8 R248 10K R248 10K VR4 100 POT Murata PV36Y101C01 PV37W VR4 100 POT Murata PV36Y101C01 PV37W 1 3 2 R302 10K R302 10K Q10 BSS138LT1 SOT 23 Q10 BSS138LT1 SOT 23 R247 10K R247 10K D21 LED 0603 Green D21 LED 0603 Green R246 10K R246 10K R301 10K R301 10K SW5 SW PUSHBUTTON Panasonic EVQP2H02B SW5 SW PUSHBUTTON Panasonic EVQP2H02B D28 LED 0603 Green D28 LED 0603 Green D18 LED 0603 Green D18 LED ...

Страница 41: ...0402 R229 49_9 0402 R226 2K 0402 R226 2K 0402 R106 10 0402 R106 10 0402 R103 33 R103 33 C194 0 01uF 0402 C194 0 01uF 0402 1 2 R219 2K 0402 R219 2K 0402 1 2 1 2 3 6 4 5 7 8 RJ45 J43 RJ 45 Belfuse 0826 1A1T 23 1 2 3 6 4 5 7 8 RJ45 J43 RJ 45 Belfuse 0826 1A1T 23 MDIA 10 MDACT 12 MDIA 11 SHLD1 19 MDIB 4 MDIB 5 MDBCT 6 MDIC 3 MDCCT 1 MDIC 2 MDID 8 MDDCT 7 MDID 9 SHLD2 20 LED1 13 LED1 14 LED2 15 LED2 16...

Страница 42: ...PA5 FIFOADR1 45 PA6 PKTEND 46 PA7 FLAGD SLCS 47 GND 48 RESET 49 VCC 50 WAKEUP 51 PD0 FD8 52 PD1 FD9 53 PD2 FD10 54 PD3 FD11 55 PD4 FD12 56 C130 0 001uF 0402 C130 0 001uF 0402 1 2 TP31 TP31 TP8 TP8 6 O I C C V 7 O I C C V Pin name sequence PL 640 1200 2280 U10B MachXO_2280_fpBGA256 6 O I C C V 7 O I C C V Pin name sequence PL 640 1200 2280 U10B MachXO_2280_fpBGA256 NC PL2A PL2A PLL1T_FB E4 NC PL2B ...

Страница 43: ...741X083 RN13 33 741X083 1 2 3 4 8 7 6 5 RN10 33 741X083 RN10 33 741X083 1 2 3 4 8 7 6 5 C158 0 01uF 0402 C158 0 01uF 0402 1 2 BANK 3 BANK 2 LFXP217 fpBGA484 U8C BANK 3 BANK 2 LFXP217 fpBGA484 U8C PR48B VREF2_3 V18 PR48A VREF1_3 V17 PR47B V19 PR47A W19 PR46B W20 PR46A W22 PR45B Y19 PR45A Y20 PR44B T17 PR43B V20 PR44A R16 PR43A U20 PR42B V22 PR42A U21 PR41B R17 PR41A R18 PR40B P17 PR39B U22 PR40A P1...

Страница 44: ...5R 0805 1 2 GND6 CON1 GND6 CON1 1 TP19 TP19 TP34 TP34 LFXP217 fpBGA484 U8E LFXP217 fpBGA484 U8E 30 or 40 device AB21 NC H8 30 or 40 device R15 NC R8 30 or 40 device U19 30 or 40 device U17 30 or 40 device U18 VCC N9 VCC P10 VCC J10 VCC J11 VCC J12 VCC P11 VCC P12 VCC J13 VCC K14 VCC P13 VCC K9 VCC L14 VCC L9 VCC M14 VCC M9 VCC N14 VCCAUX H11 VCCAUX H12 VCCAUX L15 VCCAUX L8 VCCAUX M15 VCCAUX M8 VCC...

Страница 45: ...uF Ceramic X5R 0603 1 2 D6 LED 0603 Green D6 LED 0603 Green R133 10K 0402 R133 10K 0402 C220 0 1uF 0402 C220 0 1uF 0402 R127 100 R127 100 TP91 TP91 R131 10 0402 R131 10 0402 D30 1N5820 267 05 D30 1N5820 267 05 D9 LED 0603 Green D9 LED 0603 Green TP97 TP97 D12 LED 0603 Green D12 LED 0603 Green Q9 Si4840DY SO 8 Q9 Si4840DY SO 8 5 4 1 6 2 3 7 8 J50 BANANA JACK J50 BANANA JACK S 1 R265 4 7K R265 4 7K ...

Страница 46: ...5R 0805 1 2 C44 0 01uF 0402 C44 0 01uF 0402 1 2 R111 42 2K 1 YAGEO 0402 R111 42 2K 1 YAGEO 0402 R279 2 0M 1 YAGEO 0603 R279 2 0M 1 YAGEO 0603 C43 1800p 0402 C43 1800p 0402 1 2 C29 1800p 0402 C29 1800p 0402 1 2 L2 6 2uH Sumida CDRH6D38 6R2 L2 6 2uH Sumida CDRH6D38 6R2 1 2 R281 10K R281 10K U14 TPS51116PWP U14 TPS51116PWP VTTGND 3 VTTSNS 4 GND 5 MODE 6 VTTREF 7 COMP 8 PGND 16 CS 15 V5IN 14 PGOOD 13 ...

Страница 47: ...A Title Size Document Number Rev Date Sheet of B Placement Dimension 6 0 x12 0 C 14 14 Title Size Document Number Rev Date Sheet of B Placement Dimension 6 0 x12 0 C 14 14 Title Size Document Number Rev Date Sheet of B Placement Dimension 6 0 x12 0 C 14 14 Lattice Semiconductor Corporation Placement and Dimension 6 x 12 ...

Страница 48: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Lattice LFXP2 17E H EVN ...

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