Lattice Semiconductor LatticeECP2M SERDES, Руководство пользователя

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LatticeECP2M SERDES
Lattice Semiconductor Evaluation Board User’s Guide
• ORCAstra Demonstration Software interface via standard ispVM JTAG connection
• Various high-speed layout structures
• User-defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation
board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the
board. Figure 2 shows the functional partitioning of the board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
Figure 2. LatticeECP2M SERDES Evaluation Board Block Diagram
LatticeECP2M
672 fpBGA
8 LVDS Paired SMAs
for Demo of LVDS
I/O Performance
Clock Management
ispClock
SMA Clock
Inputs/Oscillator
PCI Express x1
Edge Fingers
(LatticeECP2M-50 Only)
LatticeECP2M-50 Only
General Purpose
I/O: Switches
& LEDs
1 SERDES
Channel
SFP Cage
16 SMAs/
4 SERDES
Channels
(SRIO x1, x4),
XAUI
2 SERDES
Channels
SATA Interface
DDR2 Memory
Component
ispVM/JTAG
FPGA Loader
SPI Flash Devices