Lattice Semiconductor LatticeECP2M SERDES, Руководство пользователя

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LatticeECP2M SERDES
Lattice Semiconductor Evaluation Board User’s Guide
Ordering Information
Description Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP2M35 SERDES Evaluation Board
(Non-RoHS, Obsolete)
LFE2M35E-S-EV 10
LatticeECP2M50 SERDES Evaluation Board
(Non-RoHS, Obsolete)
LFE2M50E-S-EV 10
LatticeECP2M50 SERDES Evaluation Board
(RoHS Compliant)
LFE2M50E-S-EVN
Known Issues
The current silkscreen markings by J28 and J31 are incorrectly labeled. They should be labeled 3G OUT CH3.
SATA Host interface (CN1) – Receive data must be polarity-inverted in FPGA design for correct connection.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: techsupport@latticesemi.com
Internet: www.latticesemi.com
Revision History
Date Version Change Summary
December 2006 01.0 Initial release.
December 2006 01.1 Includes new SERDES schematic in Appendix A.
March 2007 01.2 Added Ordering Information section.
April 2007 01.3 Added important information for proper connection of ispDOWNLOAD
(Programming) Cables.
May 2007 01.4 Updated SW6D switch information in FPGA Test Pins table.
February 2008 01.5 Updated FPGA Clock Management text section and added Clock
Source Connection Variations table.
Updated SERDES Connectors table.
Added Known Issues section.
Updated SERDES schematic in Appendix A.
January 2009 01.6 Updated ordering information.
May 2010 01.7 Updated Known Issues section.
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