Lattice Semiconductor LatticeECP2M SERDES, Руководство пользователя

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LatticeECP2M SERDES
Lattice Semiconductor Evaluation Board User’s Guide
Test Pad Array
A 5 x 12 array of test pads are provided for the user to utilize for test points. This array provides 48 general I/O con-
tacts and 12 ground points.
Table 13. Test Pad Array BGA Reference
1 2 3 4 5 6 7 8 9 10 11 12
13 14 15 16 17 18 19 20 21 22 23 24
25 26 27 28 29 30 31 32 33 34 35 36
37 38 39 40 41 42 43 44 45 46 47 48
49 50 51 52 53 54 55 56 57 58 59 60
Test Points Array on Component Side
AA20 V17 W20 AC25 AC23 AD26 AB21 AC22 AD12 AF12 W14 AB13
AA13 AE9 AF9 AB6 E23 E24 P26 P25 U21 U19 V21 J2
GND GND GND GND GND GND GND GND GND GND GND GND
K7 J6 K5 L5 P5 N6 P4 R3 W5 Y4 U8 W6
G7 G8 E6 D5 G12 C8 E13 H17 E14 G17 D17 E17
High Speed Test Point
DP1
(see Appendix A, Figure 9)
General-purpose FPGA pins are available to a differential test pad. These connections allow a high-impedance
probe to measure the performance of a coupled- differential output buffer pair.
DDR2 Memory
U18
(see Appendix A, Figure 10)
The LatticeECP2M SERDES Evaluation Board is equipped with an 84-ball BGA DDR2 SDRAM memory device
such as the Micron MT47H16M16BG-3 device. The DDR2 memory interface includes a 16-bit wide device. The
evaluation board includes termination of address and command signals. It includes all power and external compo-
nents needed to demonstrate the memory controller of the LatticeECP2M device.