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LatticeECP2M SERDES
Lattice Semiconductor
Evaluation Board User’s Guide
Introduction
This user’s guide describes the LatticeECP2M™ SERDES Evaluation Board featuring the LatticeECP2M FPGA.
This stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applica-
tions that require high-speed SERDES interfaces. The board also includes a PCI Express x1 edge for future expan-
sion. Please note the PCI Express x1 edge is only connected if the board is populated with the LatticeECP2M-50
or larger FPGA.
The evaluation board includes provisioning to connect four high-speed SERDES channels via SMA connectors to
test and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete customer evaluations of the LatticeECP2M
FPGA. The intended use of this guide is to be referenced in conjunction with evaluation design tutorials to demon-
strate the LatticeECP2M FPGA.
Figure 1. LatticeECP2M SERDES Evaluation Board
Board Features
• LatticeECP2M FPGA in 672-ffBGA package. Default device is LFE2M35E-6FF672C.
• Four SERDES high-speed channels interfaced to SMA test points and clock connections SERDES interface to
x1 PCI Express edge fingers (PCI Express x1 edge available with LatticeECP2M-50 or larger FPGA only)
• DDR2 memory device
• SFP Transceiver cage and associated interface (available with LatticeECP2M-50 or larger FPGA only)
• SATA-like connections to SERDES channels (available with LatticeECP2M-50 or larger FPGA only)
• Power connections and power sources
• ispVM
®
programming support
• On-board and external reference clock sources
– Interchangeable clock oscillators
– On-board reference clock management using Lattice ispClock™ devices
