Lattice Semiconductor LatticeECP2M SERDES, Руководство пользователя

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LatticeECP2M SERDES
Lattice Semiconductor Evaluation Board User’s Guide
Table 5. SMA Clock Input
SMA Signal
J35 U2 Ref Input
J36 U2 Reference - Input
U2 is an ispClock5620A clock generator that allows designers to implement clock distribution networks supporting
multiple, synchronized output frequencies using a single device. By integrating a Phase-Locked Loop (PLL) along
with multiple output dividers, the ispClock5620A can derive up to five separate output frequencies from a single
input reference frequency. PAC-Designer
®
software (available for download from the Lattice web site at www.lattic-
esemi.com/pac-designer) is used to program the ispClock features.
ispClock supports reference clocks in the range of 10 to 320 MHz. The duty cycle of the clock source does not
need to be 50%; the only requirement is that both the HIGH and LOW times of this signal must be 1.25ns or longer.
The following standards are supported with either minimal or no external components: LVTTL, LVCMOS, SSTL2,
SSTL3, HSTL, LVDS and LVPECL.
When the ispClock5620A is in a LOCKED state, the LOCK output pin goes LOW. The LOCKN pins are connected
to amber LED D13 and will illuminate when the LOCKN pin goes low. The lock detector has two operating modes;
phase-lock mode and frequency lock mode. In phase-lock mode, the LOCK signal is asserted if the phases of the
reference and feedback signals match. In frequency-lock mode the LOCK signal is asserted when the frequencies
of the feedback and reference signals match.
U2 is controlled by SW4 or from a predefined connection to U1 (LatticeECP2M). The DIP switch controls the isp-
Clock device. The reference clock selection and device reset is controlled using the switches. The switches that
control the ispClock outputs can be synchronously controlled by the SGATE output on a bank-by-bank basis or tri-
stated on an output-by-output basis using the OEXb and OEYb inputs. All outputs may be tri-stated by bringing the
GOEb input high.
The VCCO voltage is board-connected to 2.5V or 3.3V based on the on-board connection of FB21 or FB22.
The output clocks of U2 are routed to devices to provide system level clocking. These pre-defined board clocks are
routed to input LatticeECP2M input clock pins for SERDES reference clocks, primary clocks, PLL inputs and DLL
inputs as well as connection to a SMA (J34). This SMA is 50-ohm terminated for off-board interconnection to test
equipment.
A clock input to the ispClock device can be provided from the PCI Express edge-fingers. This is accomplished by
configuring the on-board resistor jumpers R79 and R80 (see Appendix A, Figure 5).
The board has various component stuffing options to provision specific clock source variations. Table 6 outlines the
need to open or short connections on the board as well as required terminations for proper signal quality.
Table 6. Clock Source Connection Variations
Clock Source R67 R68 R69 R70 R100 R101 R215
Default short short 50-ohm 50-ohm short short 100-ohm
Y1 or Y2 Clock Source open open open open short short open
J14/J15 CML or LVDS source short short 50-ohm 50-ohm open open open
Core Ref Clock open open don’t care don’t care don’t care don’t care don’t care