Kontron cPCI-MXS64, Техническое справочное руководство

Страница: 75 / 132

Installing the Board
3-33
3.5.2.4. Ethernet 1 Interface
Signal Pin Assignation Description
LAN0:ETX+ A16 Ethernet 1 High Transmit Data line
LAN0:ETX- B16 Ethernet 1 Low Transmit Data line
LAN0:ERX+ C16 Ethernet 1 High Receive Data line
LAN0:ERX- D16 Ethernet 1 Low Receive Data line
3.5.2.5. Hot Swap HA (High Availability) Signals
Signal Pin Assignation Description
BDSEL S6-S8
C11, E20, B25 Board Select, one of the shortest pins (the last to mate
and the first to break contact).
HEALTHY S5-S8
C9, D15, C22, C25 Used to acknowledge the health of the board
PCIRST S5-S8
E9, E15, A25, D25 Used to indicate the CompactPCI Bus reset signal
3.5.2.6. IDE 1 Interface
Signal Pin Assignation Description
IDE1:RST# A17
IDE1:0-15 B20, E19, C19, A19,
D18, B18, E17, C17,
D17, A18, C18, E18,
B19, D19, A20, C20 Sec. Disk Data – These signals are used to transfer
data to or from the IDE device.
IDE1:REQ A21 Sec. Disk DMA Request - This signal is directly driven
from the IDE device DMARQ signal. It is asserted by
the IDE device to request a data transfer.
IDE1:IOW# C21 Sec. Disk I/O Write – In normal IDE mode, this is the
command to the IDE device that it may latch data from
SDD lines.
IDE1:IOR# E21 Sec. Disk I/O Read – In normal IDE mode, this is the
command to the IDE device that it may drive data on
SDD lines.
IDE1:IORDY B22 Sec. I/O Channel Ready – In normal mode, this input
signal is driven directly by the corresponding IDE
device IORDY signal.
IDE1:DACK# D22 Sec. DMA Acknowledge – This signal directly drives
the IDE device /DMACK signal. It is asserted to
indicate to IDE DMA slave devices that a given data
transfer cycle is a DMA data transfer cycle.
IRQ15 E22
IDE1:IO16 A23
IDE1: A 0-2 D23, B23, E23 Sec. Disk Address – These signals indicates which
byte in either the ATA command block or control block
is being addressed.
IDE1:CS1#,
IDE1 :CS3# A24, B24 Secondary Chip Select - For ATA control register.
SEC-PD1 C24
/FAL1 E24
IDE 1 (IDE 1) is assigned to the Secondary IDE logical interface. It supports directly two
IDE devices configured as master and slave devices.