CP307
Power Considerations
ID 34424, Rev. 3.0
Page 5 - 5
P R E L I M I N A R Y
5.1.3.2
Power-Up Sequence
The +5 VDC output level must always be equal to or higher than the +3.3 VDC output during
power-up and normal operation.
Both voltages must reach their minimum in-regulation level not later than 20 ms after the output
power ramp start.
5.1.3.3
Tolerance
The tolerance of the voltage lines is described in the CPCI specification (PICMG 2.0 R3.0).The
recommended measurement point for the voltage is the CPCI connector on the CPU board.
The following table provides information regarding the required characteristics for each board
input voltage.
The output voltage overshoot generated during the application (load changes) or during the
removal of the input voltage must be less than 5% of the nominal value. No voltage of reverse
polarity may be present on any output during turn-on or turn-off.
Table 5-3: Input Voltage Characteristics
VOLTAGE
NOMINAL VALUE
TOLERANCE
MAX. RIPPLE (p-p)
REMARKS
5 V
+5.0 VDC
+5%/-3%
50 mV
Main voltage
3.3 V
+3.3 VDC
+5%/-3%
50 mV
Main voltage
+12 V
+12 VDC
+5%/-5%
240 mV
Not required
-12 V
-12 VDC
+5%/-5%
240 mV
Not required
V I/O (PCI)
signalling voltage
+3.3 VDC or +5 VDC
+5%/-3%
50 mV
depends on board
version
GND
Ground, not directly connected to potential earth (PE)
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