Configuration
CP307
Page 4 - 18
ID 34424, Rev. 3.0
P R E L I M I N A R Y
4.5.10
Delay Timer Control/Status Register
The delay timer enables the user to realize short, reliable delay times. It runs by default and
does not start again on its own. It can be restarted at anytime by writing anything other than a
’0’ to the delay timer control/status register. The hardware delay timer provides a set of outputs
for defined elapsed time periods. The timer outputs reflected in the Delay Timer Control/Status
Register are set consecutively and remain set until the next restart is triggered again.
Since the timer width and thus the availability of outputs varies over different implementations,
it is necessary to be able to determine the timer capability. Therefore, writing a ’0’ to the Delay
Timer Control/Status Register followed by reading indicates the timer capability (not the timer
outputs). For example, writing 0x00 and then reading 0xFF results in a 8-bit wide timer register.
This status register mode can be switched off to normal timer operation by writing anything oth-
er than a ’0’ to this register.
Table 4-15: Delay Timer Control/Status Register
REGISTER NAME
DELAY TIMER CONTROL / STATUS REGISTER
SIZE
ADDRESS
0x28F
8 bits
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LSB
CONTENT
DTC7
DTC6
DTC5
DTC4
DTC3
DTC2
DTC1
DTC0
DEFAULT
0
0
0
0
0
0
0
0
ACCESS
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BIT
NAME
DESCRIPTION / FUNCTION
7 - 0
DTC[7:0] The hardware delay timer is operated via one simple 8-bit control/status register. During
normal operation, each of the 8 bits reflects a timer output which means defined elapsed
time period after the last restart according to the following bit mapping:
DTC[7:0] Value
Accuracy
Bit 7:
1 ms
< + 0.04%
Bit 6:
500 µs
< + 0.08%
Bit 5:
250 µs
< + 0.16%
Bit 4:
100 µs
< + 0.4%
Bit 3:
50 µs
< + 0.8%
Bit 2:
10 µs
< + 4%
Bit 1:
5 µs
< + 8%
Bit 0:
1 µs
< + 40%
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