CP307
Configuration
ID 34424, Rev. 3.0
Page 4 - 17
P R E L I M I N A R Y
4.5.9
Rear I/O GPIO Register
The Rear I/O GPIO Register controls the General Purpose outputs and holds the status of the
General Purpose inputs. This register can only be used if the Rear I/O configuration bits
RCFG[1:0] in Table 4-9 are set to “01” (i.e. if the GPIO function is enabled).
Table 4-14: Rear I/O GPIO Register
REGISTER NAME
REAR I/O GPIO REGISTER
SIZE
ADDRESS
0x28E
8 bits
BIT POSITION
MSB
7
6
5
4
3
2
1
0
LSB
CONTENT
GPO2
GPO1
GPO0
GPI4
GPI3
GPI2
GPI1
GPI0
DEFAULT
0
0
0
1
1
1
1
1
ACCESS
R/W
R/W
R/W
R
R
R
R
R
BIT
NAME
DESCRIPTION / FUNCTION
7
GPO2
GPO2 signal (3.3V TTL):
0 Output low
1 Output high
6
GPO1
GPO1 signal (3.3V TTL):
0 Output low
1 Output high
5
GPO0
GPO0 signal (3.3V TTL):
0 Output low
1 Output high
4
GPI4
GPI4 signal (3.3V TTL):
0 Input low
1 Input high
3
GPI3
GPI3 signal (3.3V TTL):
0 Input low
1 Input high
2
GPI2
GPI2 signal (3.3V TTL):
0 Input low
1 Input high
1
GPI1
GPI1 signal (3.3V TTL):
0 Input low
1 Input high
0
GPI0
GPI0 signal (3.3V TTL):
0 Input low
1 Input high
Note ...
The CP307 provides pull-up resistors on the Rear I/O signal pins GPI[4:0] which
leads to the default setting “input high” if the inputs are not connected.
The General Purpose Inputs support 3.3V TTL signalling only.
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