CP307
Preface
ID 34424, Rev. 3.0
Page ix
P R E L I M I N A R Y
List of Tables
1-1
System Relevant Information .................................................................... 1 - 6
1-2
CP307 4HP Version Main Specifications ................................................. 1 - 10
1-3
Standards ................................................................................................ 1 - 16
1-4
Related Publications ............................................................................... 1 - 17
2-1
Processors Supported on the CP307 ........................................................ 2 - 4
2-2
Maximum Power Dissipation of the Processors (CPU only) ...................... 2 - 4
2-3
CPU Frequency in the Various SpeedStep® Modes ................................. 2 - 4
2-4
Supported Memory Configurations ............................................................ 2 - 5
2-5
SMBus Device Addresses ......................................................................... 2 - 9
2-6
EEPROM Address Map ........................................................................... 2 - 10
2-7
CompactFlash Connector Pinout ............................................................. 2 - 11
2-8
POST Code Indication ............................................................................. 2 - 12
2-9
USB Connectors J9 and J10 Pinout ........................................................ 2 - 13
2-10 D-Sub VGA Connector J6 Pinout ............................................................ 2 - 14
2-11 Pinouts of J11A/B Based on the Implementation ..................................... 2 - 15
2-12 SATA Connector J4 Pinout ...................................................................... 2 - 16
2-13 Coding Key Colors .................................................................................. 2 - 17
2-14 CompactPCI Bus Connector J1 Pinout ................................................... 2 - 18
2-15 64-bit CompactPCI Bus Connector J2 Pinout (CP307 Front I/O Vers.) .. 2 - 19
2-16 Rear I/O CompactPCI Bus Connector J2 Pinout (CP307 Rear I/O Vers.) 2 - 21
2-17 GPIO Signal Description ......................................................................... 2 - 22
2-18 SATA Port Features ................................................................................. 2 - 24
4-1
Clearing BIOS CMOS Setup ..................................................................... 4 - 3
4-2
Legacy Interrupt Setting ............................................................................ 4 - 4
4-3
PCI Interrupt Routing ................................................................................. 4 - 5
4-4
Memory Map for the 1st Megabyte ............................................................ 4 - 6
4-5
I/O Address Map ........................................................................................ 4 - 7
4-6
Watchdog Timer Control Register ............................................................. 4 - 9
4-7
Hardware and Logic Revision Index Register ......................................... 4 - 10
4-8
Reset Status Register .............................................................................. 4 - 11
4-9
I/O Status Register .................................................................................. 4 - 12
4-10 I/O Configuration Register ....................................................................... 4 - 13
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com