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COMe-bEP7 Module User Guide
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* After expiring the counter or triggering the stage action will be set to “No action”.
The purpose is to allow a one-time delay before starting the actual time. WDT
signal (mode 1101b) asserted after stage timeout, not after stage triggering.
9.4.
WDT Signal
Pin B27 on COM Express® Connector offers a signal that can be asserted when a
watchdog timer has not been triggered within time. It can be configured to any of
the three stages. Reassertion of the signal is done automatically after reset. If de-
assertion during runtime is necessary, please ask your Kontron technical support
for further help.
9.5.
Power capping settings
Possibility to set a power level below actual CPU TDP. Refer to AMD EPYC processor
specification.
Present options available in BIOS menu are:
1-
Advanced -> AMD CBS -> NBIO Common Options -> cTDP Control
When set to [Auto], the fused maximum cTDP of the SoC is used.
When set to [Manual], can set customized cTDP value with option “cTDP”.
2-
Advanced -> AMD CBS -> NBIO Common Options -> cTDP
Customized cTDP value (in Watts).
9.6.
CPU Core Characteristics
The SP4/SP4r2 package is based on the AMD “Zen” CPU architecture.
9.6.1.
Core P-States
The “Zen” core is designed to support as many as three performance states (P-
states). P-state count, voltage, and frequency selection are defined by the specific
processor model and optimized by voltage spread. The voltage for each P-state is
optimized for maximum power savings between P-states at the highest frequency
for that state.
9.6.2.
Core C-States
C-states are processor core power states. C0 is the operational state in which
instructions are executed, while higher numbered C-states (C1, C2, and so forth) are
low-power states in which the core is idle. C-states are exposed through ACPI
objects and can be dynamically requested by software.
The "Zen" core is designed to support as many as three AMD specified C-states: I/O-
based C-states 0, 1, and 2.
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