Kontron COMe-bEP7, Руководство пользователя

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COMe-bEP7 Module User Guide
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Table 7: PCIe Biffurcation Table
Function Second level Sub-
Screen / Description Description
COMe PCIE[0:7] Lanes Limitation to maximum 7 ports.
Link Width at PCIE0 [Disabled, x1, 2, x4,
x8
]
Number of PCIE lanes for Link starting at COMe PCIE0.
Link Width at PCIE1
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE1.
Link Width at PCIE2
[
Disabled
, x1, x2 ]
Number of PCIE lanes for Link starting at COMe PCIE2.
Link Width at PCIE3
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE3.
Link Width at PCIE4
[
Disabled
, x1, x2, x4 ]
Number of PCIE lanes for Link starting at COMe PCIE4.
Link Width at PCIE5 [
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE5.
Link Width at PCIE6
[
Disabled
, x1, x2 ]
Number of PCIE lanes for Link starting at COMe PCIE6.
Link Width at PCIE7 [
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE7.
COMe PCIE[8:15] Lanes
SP4 only
Limitation to maximum 7 ports.
Link Width at PCIE8
[Disabled, x1, 2, x4,
x8
]
Number of PCIE lanes for Link starting at COMe PCIE8.
Link Width at PCIE9
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE9.
Link Width at PCIE10 [
Disabled
, x1, x2 ]
Number of PCIE lanes for Link starting at COMe PCIE10.
Link Width at PCIE11
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE11.
Link Width at PCIE12 [
Disabled
, x1, x2, x4 ]
Number of PCIE lanes for Link starting at COMe PCIE12.
Link Width at PCIE13
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE13.
Link Width at PCIE14
[
Disabled
, x1, x2 ]
Number of PCIE lanes for Link starting at COMe PCIE14.
Link Width at PCIE15
[
Disabled
, x1 ]
Number of PCIE lanes for Link starting at COMe PCIE15.
COMe PCIE[16:31] Lanes
Link Width at PCIE16 [Disabled, x4, x8,
x16
]
Number of PCIE lanes for Link starting at COMe PCIE0.
Link Width at PCIE20
[
Disabled
, x4 ]
Number of PCIE lanes for Link starting at COMe PCIE1.
Link Width at PCIE24 [
Disabled
, x4, x8 ]
Number of PCIE lanes for Link starting at COMe PCIE2.
Link Width at PCIE28
[
Disabled
, x4 ]
Number of PCIE lanes for Link starting at COMe PCIE3.