18 ---- Various Settings
6.11.2
Mobile
DDR
MEMORY
The Mobile DDR MEMORY used for this product is linked to the CSD0 address space of the Enhanced SDRAM Controller
(ESDCTL). This product is designed to operate under HCLK of 106 MHz. The DDR
memory serves as the SSTL interface
whilst the ESDCTL and Mobile DDR MEMORY are 1.8V LVCMOS. However, they will be initialized in the same manner as
the DDR memory. In addition, it is possible to set the PIN driving power for i.MX31 as follows: normal:2mA, high
：
6mA, and
max:8mA. This can be set with the SW_PAD_CTL Register in the IOMUXC module. Set this pin driving power before setting
up ESDCTL. From the nature of this board, pins should be set to active-high.
The SW_PAD_CTL Register affords for 32 bits for accessing, and three pins can be assigned for each address. This
assignment is made as 0
：
8 bits, 10:18 bits, and 20:28 bits and the 1st and 2nd bits among them are used for setting the driving
power.
Example active-high drive setting of SD29, SD30 and SD31 pins
address
：
0x43FA_C28c
data: 0x1234_8D23
In this way set all the ESDCTL signals.
The ESDCTL-related settings include the controller-side modes, pre-charge, Auto-Refresh×
８
cycles, and memory-side modes.
These settings can be initialized with the registers of ESDCTL0
0xB800_1000, ESDCFG0
0xB800_1004, and ESDMISC
0xB800_1010, respectively. Setting values are that follow:
ESDCFG0 address
：
0xB800_1004
data: 0x0079_D72A
tMRD
2 cycles
、
tWR 2 cycles
、
tRAS 6 cycles
、
tRRD 2 cycles
、
tCAS 3 cycles
tRP 3 cycles
、
tRCD 3 cycles
、
tRC 10 cycles
、
tWTR 2 cycles
、
tXP 4 cycles
Precharge
ESDCTL0 address
：
0xB800_1000
data: 9210_0000
31 SDE:1 Controller Enable
、
30–28 SMODE:1 Precharge Command
MEMORY
address
：
0x8000_0F00
data: 0
After setting to ESDCTL0, access the memory to issue the respective command.
Auto-Refresh
ESDCTL0 address
：
0xB800_1000,a2100000
31 SDE:1 Controller Enable
、
30–28 SMODE:2 Auto-Refresh Command
MEMORY
address
：
0x8000_0000,0
MEMORY
address
：
0x8000_0000,0
Auto-Refresh
×2
Load Mode Register
ESDCTL0 address
：
0xB800_1000,b2226080
31 SDE:1 Controller Enable
、
30–28 SMODE:3 Load Mode Register Command
、
26–24 ROW:2 13bit
、
21–20 COL:2 10bit17–16 DSIZ:2 32-bit
、
15–13 SREFR
：３
7.81
μ
s
、
7 BL:1 Burst Length 8
、
5–0 PRCT:0 Disabled
MEMORY
address
：
0x8000_0033,0
6-4 CL:3 CAS Latency3
、
3 BT:0 Burst Type Sequential
、
2–0 BL:3 Burst Length 8
MEMORY
address
：
0x8400_0020,0
Содержание KZM-ARM11-01
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