40 ---- Connector Pins Assignment
25 A19
AF12
75
CPU_DTE2_DCD
B13
*1
26 A20
AF11
76
CPU_SCK5
D3
27 A21
AF10
77
CPU_UART2_RTS
B14
*1
28 A22
AF9
78
CPU_SFS5
A3
29 A23
AF8
79
CPU_UART2_RXD
A13
*1
30 A24
AF7
80
CPU_SRXD5
31 GND
81
CPU_DTE2_DSR
A12
*1
32 GND
82
CPU_STXD5
C5
33 A25
AF6
83
CPU_DTE2_RI
G12
*1
34 OEn
AB25
84
CPU_USB_BYP
A9
35 RW
AB22
85
CN_TDI/D0
*4
36 EBN0
W21
86
CPU_USB_OC
C10
37 EBN1
Y24
87
CN_TDO/CONF_DONE
*4
38 LBAn
AE22
88
CPU_USB_PWR
B10
39 CSN0
AE23
89
RSTn
*5
40 CSN1
AF23
90
CN_RSTn_IN
*5
41 CSN4
AF24
91
GND
42 CSN5
AF22
92
GND
43 D0
AB2
93
+5V
44 D1
Y3
94
+3.0V
45 D2
AB1
95
+5V
46 D3
W6
96
+3.0V
47 D4
AA2
97
+5V
48 D5
V7
98
+3.0V
49 D6
AA1
99
+5V
50 D7
W3
100
+3.0V
Table10 CN7 Pins Assignment
*1 This is a UART2 signal that shares IrDA interface with CN5. In order to use these signals it is necessary to set the rotary
switch (RSW1) properly. Refer to the list of settings presented in this Manual.
*
2
These signals are connected to FPGA. M_WEN0,1 is the result of ORing between RW and EBN.
*3 GPIO pin of i.MX31. Available as one of the i.MX31 interrupts.
*4 Connected to FPGA. Functions as RS-232C (auxiliary).
Содержание KZM-ARM11-01
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