BOARD Controller ---- 33
NAND Flash Operation Configuration1
Address :
0xB620
0E1A
Access
: 16bit Read/Write
Bit No.
Description
15-7 Reserved
6
Resetting controller. Resets NAND Flash Control.
0: Normal
1: Reset
5 Reserved
4 INT
mask
0: Interrupt enabled
1: Interrupt disabled
5 Reserved
3 ECC
Enable
0: ECC is invalid.
1: Performs ECC-based transmission.
2 Spare
Enable
0: Both Main and Spare are accessible.
1: Only Spare is accessible.
1-0 Reserved
NAND Flash Operation Configuration2
NAND Flash signals are controlled with these registers.
Address :
0xB620
0E1C
Access
: 16bit Read/Write
Bit No.
Description
15
An interrupt signal. Writing 0 clears this bit. (Writing 1has no effect.)
0: Operation in progress
1: Operation completed
14-7 Reserved
6-3
NAND Flash Data Output FDO
001 One page data out
010 NAND Flash ID data out
100 NAND Flash Status Register data out
2
NAND Flash Data Input FDI
1 NAND Flash data input operation
1
NAND Flash Address Input FADD
1 NAND Flash Address input operation
0
NAND Flash Command Input FCMD
1 Allow NAND Flash Command input operation
Each of the FDO, FDI, FADD, and FCMD bits will be automatically reset to 0 after the operation is completed.
ONE page
:
Page size will be 64 (Spare) bytes for the case of SP_EN=1 and 2048 (Main) + 64 (Spare) bytes for the case of
SP_EN=0.
Содержание KZM-ARM11-01
Страница 1: ...ARM11 Embedded Evaluation Board KZM ARM11 01 Operation Manual Kyoto Microcomputer Co Ltd ...
Страница 93: ......