BOARD Controller ---- 31
8.2 NAND FLASH control
The NAND FLASH controller provides controls over NAND Flash (IC7) and NAND Flash expansion connector.
This NAND FLASH control is not part of the i.MX31 functions, but has been installed as an external FPGA. It is
provided with a 2Kbytes MAIN Buffer RAM and 64-bytes SPAR Buffer RAM. Read/write of NAND FLASH
memory will be performed via this Buffer RAM.
Main Buffer address : 0xB620 0000-0xB620 07FF
Spar Buffer address : 0xB620 0800-0xB620 083F
ADD
Used for writing an address to FLASH device. Setting the FADD bit to 1 allows the value of this register to be
written in the FLASH device.
Address :
0xB620
0E06
Access
: 16bit Read/Write
Bit No.
Description
15-8 Reserved
7-0 NAND
Flash
Address
CMD
Used for writing a command to the FLASH device. Setting the FCMD bit to 1 allows the value of this register to be
written in the FLASH device.
Address :
0xB620
0E08
Access
: 16bit Read/Write
Bit No.
Description
15-8 Reserved
7-0 NAND
Flash
Command
NAND Flash Write Protection
Write-protect commands. The lock condition means that /WP signals are active for the FLASH device.
Address :
0xB620
0E12
Access
: 16bit Read/Write
Bit No.
Description
15-3 Reserved
2-0
Write Protection Command
100 Unlock NAND Flash
010 Lock all NAND Flash
001 Lock-tight locked
Содержание KZM-ARM11-01
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