16 ---- Various Settings
6.10 Interrupt
The interrupt function of this product is implemented in such a way that the ARM1136JF-S Vectored Interrupt Controller
(AVIC), which is one of the devices of i.MX31, is connected to the interrupt input port. This AVIC can accommodate a
maximum of 64 interrupt sources. Interrupts from each of i.MX31 peripherals are assigned to this AVIC, and the GPIO pins
are used for external interrupts. In this product each device is connected via GPIO to the IRQ or FIQ port of i.MX31 as shown
below. For details of each interrupt setting refer to the i.MX31 Manual.
The GPIO1_1 interrupt port for NAND, F_UART and SD is masked under the initial conditions. To make it function, set with
the registers in the FPGA Controller.
i.MX31
AVIC
GPIO1_0
GPIO1_1
GPIO1_2
GPIO1_4
GPIO1_5
nFIQ
nIRQ
Internal Peripherals
ARM1136JF-S
AVIC_IRQ
AVIC_FIQ
Fig.12
Interrupt
6.11
Memory
The External Memory Interface (EMI) of i.MX31 accommodates various types of memory devices. The dedicated built-in
controller controls these devices. Memory clock (HCLK) is generated in the CCM by dividing the clock frequency of PLL
MCU. HCLK is set to 106 MHz. Then, this clock rate will be used for setting memory access cycles. You may see “AHB
clock” in the i.MX31 Manual, however, the memory clock is always referred to as HCLK in this manual.
This product employs an NOR-type FLASH memory and Mobile DDR memory.
The setting method of each memory is described in the following.
These settings can be kept enabled while PARTNER-Jet is connected if an appropriate description has been made in
JETARM.CFG before starting the debugger. Make use of the sample settings prepared as the following file contained in the
PARTNER-Jet installation folder:
¥WJETARM¥Samples¥KZM-ARM11
Содержание KZM-ARM11-01
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