Various Settings ---- 15
6.6
JTAG
/SRST and i.MX31 Reset Signal Settings
:
SW2,3,JP12
Used to define the destination when connecting the JTAG debugger connector, /SRST. The factory default
is for connecting to the i.MX31’s POR_B.
It is configured as follows:
SW2
SW3
JP12
Fig.10
CN13, 16 JTAG Connector
JP
SW3
BUFFER
/SRST
FPGA
CPU
SW2
BUFFER
POR_B
RESET_IN_B
Fig.11
Resetting
6.7
NF_DET Setting
:
JP1
Used as the test terminal for the NAND controller. The factory default is open. This does not have to be
changed for regular operations.
6.8
USB
OTG
PWR Setting
:
JP16
Connects the power supply line of USB
OTG. The factory default is short-circuited. This does not have
to be changed for regular operations.
6.9
LCD
ENB Setting
:
JP4
Used to establish ENB pin settings for the LCD. The factory default is open-circuited. This does
not have to be changed for regular operations.
Содержание KZM-ARM11-01
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