JYTEK PCIe-69834, Руководство пользователя

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Operations 15
Table 3-3: Input Range Midscale Values
3.2.3 DMA Data Transfer
The PCIe-
69834
, a PCIe Gen 1 X 4 device, is equipped with
a 80MS/s high sampling rate ADC, generating a 640
MByte/second rate.
To provide efficient data transfer, a PCI bus-mastering DMA is
essential for continuous data streaming, as it helps to achieve full
potential PCI Express bus bandwidth. The bus-mastering control-
ler releases the burden on the host CPU since data is directly
transferred to the host memory without intervention. Once analog
input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired
data in the onboard AD Data FIFO, and then transfers the data to
a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA data
acquisition, the sampling period and the number of conversions
needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system
memory by the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, or other, it is difficult to allocate a large continuous memory
block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into
a linked list so users can transfer large amounts of data without
being limited by memory limitations. In non-scatter-gather mode,
Mi1LSB Midscale Midscale -1LSB
Bipolar
Analog
Input
0.305 mV 0 V -0.305 mV
0.153 mV 0 V -0.153 mV
0.031 mV 0 V -0.031 mV
0.015 mV 0 V -0.015 mV
Digital Code
0001 0000 FFFF