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This sets the number of CPU clocks allowed before reads and writes to DRAM are
performed.
7/6 Seven clocks leadoff for reads and six clocks leadoff for
writes.
6/5 Six clocks leadoff for reads and five clocks leadoff for writes.
7/6 Leadoff timing is the default.
When DRAM is refreshed, both rows and columns are addressed separately. This
setup item allows you to determine the timing of the transition from Row Address
Strobe (RAS) to Column Address Strobe (CAS).
3 Three CPU clock delay.
2 Two CPU clock delay.
3 CPU clocks is the default.
This sets the timing for burst mode reads from two different DRAM(EDO/FPM).
Burst read and write requests are generated by the CPU in four separate parts. The
first part provides the location within the DRAM where the read or write is to take
place while the remaining three parts provide the actual data. The lower the timing
numbers, the faster the system will address memory.
x222/x333 Read DRAM (EDO/FPM) timings are 2-2-2/3-3-3
x333/x444 Read DRAM (EDO/FPM) timings are 3-3-3/4-4-4
x444/x444 Read DRAM (EDO/FPM) timings are 4-4-4/4-4-4
x222/x333 timings is the default.
DRAM R/W Leadoff
Timing
Fast RAS# to CAS#
Delay
DRAM Read
<EDO/FPM>