Intergraph RealiZm Graphics V25, Руководство пользователя по оборудованию

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Geometry
Accelerator
PCI Bus
PCIDMA
Input/Output
FIFO
DSP IO Bus
DSP6 DSP5 DSP4 DSP3 DSP2 DSP1
Sequence Controller
Vertex Data Bus (to Z13, Z25, or V25)
The Geometry Accelerator receives OpenGL requests from the host processor through the
PCIDMA and the input/output (I/O) FIFO. The requests are routed to six independent 32-bit
floating-point DSPs, which process OpenGL requests in parallel. The output requests from
each DSP flow through dedicated ports to the Sequence Controller. The Sequence Controller
time-orders and formats the requests, and then writes them to the Z13, or Z25, or V25 input
FIFO over the dedicated Vertex data bus.
The processing performed by each of the six DSPs includes coordinate transformations,
lighting calculations, and viewport clipping. Clipping is the process of removing elements, or
pieces of elements, not contained within the viewing volume (viewport). The Geometry
Accelerator processes each element specified by OpenGL as supported by the Rasterization
Accelerator.