Intergraph RealiZm Graphics V25, Руководство пользователя по оборудованию

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DSPs
The core of the Geometry Accelerator is six state of the art digital signal processors (DSPs)
operating in parallel. These are 32-bit floating point processors, each capable of executing
120 million floating-point operations per second (MFLOPS). Each DSP contains 256 KB of
high-speed RAM. Each DSP also has an advanced I/O system with six communication ports
and ten DMA engines. This I/O system allows continual flow of data through the multiple
DSPs and to the Sequence Controller with minimal host processor overhead.
Sequence Controller
The multiple instruction multiple data (MIMD) architecture of the Geometry Accelerator
allows incoming data to be processed concurrently and independently by each of the six DSPs.
This means that the DSP that processes the first input request may not generate the first output
request. Data moves through the DSPs at different rates, depending upon the complexity of
the request.
Since the order of drawing operations must be maintained, this out of order data must be
placed back into the order that it was received. This task is the responsibility of the Sequence
Controller. The Sequence Controller receives data from each of the six DSPs via four
communication ports. The Sequence Controller time-orders the data, and then uses a DMA to
write the data directly to the Rasterization Accelerator via the Vertex data bus. The Sequence
Controller also handles some clipping, and controls the flow of data to multiple Rasterization
Accelerators for dual screen systems.