Intel SPSH4 - Server Platform - 0 MB RAM, Технические характеристики продукции

Страница: 77 / 118

SPSH4 Server SystemTechnical Product Specification
Revision 1.11
Intel reference number 10736
65
6.5.2.4 P3
P3 provides four dedicated function signals, and four implementation specific control signals, as
shown in Table 52.
Table 52: P3 Functions
Bit Name I/O Fixed
1
Function
7 RD_L O Y Read strobe. Indication from the microcontroller that the current bus cycle is
a read operation.
6 WR_L O Y Write strobe. Indication from the microcontroller that the current bus cycle is
a write operation.
5 Fan 2 I N Fan 2 tachometer input.
4 Fan 1 I N Fan 1 tachometer input.
3 INT1_L I Y Interrupt 1. Connected to the SCSI bus reset signal RST_L.
2 INT0_L I Y Interrupt 0. Connected to the 53C80S SCSI IRQ signal.
1 Reserved - N Reserved for future use.
0 HSBP_SEL I N SCSI backplane select: 0=5 x 1” LVD/SE SCSI Backplane; 1=3 x 1.6”
LVD/SE SCSI Backplane.
1. “Fixed” indicates whether the function/pin is defined by the microcontroller pinout (fixed) or implementation-
specific (not fixed).
6.6 Programming Information
This chapter describes briefly the programming and firmware information for the Hot-swap SCSI
Backplane. The information in this section is an overview only. For detailed information, refer to
Hudson/Cabrillo-2 Hot-swap Controller Interface EPS .
The firmware for the Hot-swap SCSI Backplane is stored in the Flash ROM. It is divided into two
sections; the 8KB boot block area and the 24KB operational code area. The boot block area
contains the basic IMB communication routines and the firmware transfer commands. The code
in this area is permanently stored and can only be updated if the Flash Boot Block Update
jumper is in the proper position. The operational code area contains the run-time code, including
the SCSI and SAF-TE routines, monitoring routines, and IMB routines. All code in this area can
be updated using the firmware transfer commands.