Intel SPSH4 - Server Platform - 0 MB RAM, Технические характеристики продукции

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SPSH4 Server SystemTechnical Product Specification
Revision 1.11
Intel reference number 10736
59
6.4.2.3.1 Noise Margin
•
Noise margin minimum on the Low level is 0.1 V
DD
.
•
Noise margin minimum on the High level is 0.2 V
DD
.
6.4.3 SCSI Controller
The SYM53C80S controller is an 8-bit controller. It is reset on power-up and when reset is
asserted to the backplane.
SYM53C80S access slows down the bus, it is recommended to pulse SAF-TE infrequently.
SAF_TE command processing is 2-10ms.
The features of the SCSI controller are as follows:
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Supports the ANSI X3.131-1994 standard
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Parity generation with optional checking
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No external clock required
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On-chip 48ma single-ended drivers and receivers
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Functions in both the target and initiator roles
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Direct control of all SCSI signals
•
Asynchronous data transfers of up to 5.0 MB/second
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Variety of packaging options
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SCSI protocol efficiency is directly proportional to the speed of the microprocessor
•
CMOS parts provide additional grounding and controlled fall times that reduce noise
generated by SCSI bus switching
•
SCAM Level 1 and 2 compatibility
6.4.4 Multi-Mode SCSI Termination
The SCSI-3 and SCSI-4 standards recommend the use of active termination at both ends of
every cable segment in a SCSI system with single-ended drivers and receivers.
Two Unitrode* UCC5638 devices are used for active termination that detect SE or LVD mode
and terminate appropriately.
6.5 Memory Map
This chapter describes the microcontroller memory map and individual regions of memory.
80C51 architecture allows up to 64KB of byte-addressable memory. No I/O map is provided,
since 80C51 architecture makes no distinction between memory and I/O addresses (all I/O
accesses are memory-mapped). However, four “I/O ports” available to the microcontroller are
also defined in this chapter.