S875WP1-E TPS
Maps and Interrupts
Revision 4.0
39
4.6 PCI Interrupt Routing Map
This section describes interrupt sharing and how the interrupt signals are connected between
the PCI bus connectors and onboard PCI devices. The PCI specification specifies how
interrupts can be shared between devices attached to the PCI bus. In most cases, the small
amount of latency added by interrupt sharing does not affect the operation or throughput of the
devices. In some special cases where maximum performance is needed from a device, a PCI
device should not share an interrupt with other PCI devices. Use the following information to
avoid sharing an interrupt with a PCI add-in card.
PCI devices are categorized as follows to specify their interrupt grouping:
56
INTA
: By default, all add-in cards that require only one interrupt are in this category. For
almost all cards that require more than one interrupt, the first interrupt on the card is also
classified as INTA.
57
INTB
: Generally, the second interrupt on add-in cards that require two or more interrupts
is classified as INTB. (This is not an absolute requirement.)
•
INTC
and
INTD
: Generally, a third interrupt on add-in cards is classified as INTC and a
fourth interrupt is classified as INTD.
The ICH5-R has eight programmable interrupt request (PIRQ) input signals. All PCI interrupt
sources either onboard or from a PCI add-in card connect to one of these PIRQ signals. Some
PCI interrupt sources are electrically tied together on the Server Board S875WP1-E and
therefore share the same interrupt. Table 19 shows an example of how the PIRQ signals are
routed.
For example, using Table 19 as a reference, assume an add-in card using INTB is plugged into
PCI bus connector 3. In PCI bus connector 3, INTB is connected to PIRQA, which is already
connected to the Promise PDC20319 Controller. The add-in card in PCI bus connector 3 now
shares an interrupt with the onboard interrupt source.
Table 19. PCI Interrupt Routing Map
ICH5-R PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
AGP
connector
INTA
INTB
PCI bus connector 1
INTF
INTG
INTH
INTE
PCI bus connector 2
INTG
INTF
INTE
INTH
PCI bus connector 3
INTB
INTC
INTD
INTA
LAN_10/100
INTE
ATI
Rage
XL
INTE
Promise
PD20319
Controller
INTB
NOTE
In PIC mode, the ICH5-R can connect each PIRQ line internally to one of the IRQ signals (3, 4,
5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. See Table 18 for the allocation
of PIRQ lines to IRQ signals in APIC mode.