50
Specification Update
Threading Technology enabled and has not been observed with commercially available
software.
Implication:
Due to this erratum, SMI handlers may not be able to identify the occurrence of I/O
SMIs.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN116.
PCIe Squelch Detect May be Slow to Respond During L0s Entry and
May Cause a Surprise Link Down Condition
Problem:
When entering the L0s idle state the PCIe squelch detect response may be slower than
expected. This slow response can cause the PCIe interface at the downstream port to
unexpectedly enter the L0s.FTS (Fast Training Sequence) state instead of the normal
operation which is staying in the L0s.idle state until the Tx side of the upstream port
exits squelch. This unexpected state transition may cause a recovery entry leading to a
Surprise Link Down condition.
Implication:
This erratum may cause a system hang while trying reach the L0s state.
Workaround:
A BIOS workaround has been identified. Please refer to the latest version (Revision
1.31) of the BIOS specification and release notes.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN117.
TR Corruption Due to Save/Restore x87 FPU Pointers
in SMRAM
Problem:
When the system software enables the saving/restoring of x87 FPU instruction and
data pointers in SMRAM by setting the SMM_SAVE_CONTROL MSR (3EH) bit 0 to 1, the
TR (Task Register) selector may be restored incorrectly on the exit from SMM.
Implication:
The TR selector containing incorrect data may cause unpredictable system behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN118.
PCIe Lanes Returning to The Active Power State May Cause The
System to Hang
Problem:
Under certain conditions, when the PCIe lanes come out of the S0 power savings state,
the clocks may change asynchronously leading to a system hang.
Implication:
A System hang may occur when coming out of the S0 power saving state.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN119.
Performance Monitor Events for Hardware Prefetches Which Miss The
L1 Data Cache May be Over-Counted
Problem:
Hardware prefetches that miss the L1 data cache but cannot be processed immediately
due to resource conflicts will count and then retry. This may lead to incorrectly
incrementing the L1D_PREFETCH.MISS (event 4EH, umask 02H) event multiple times
for a single miss.
Implication:
The count reported by the L1D_PREFETCH.MISS event may be higher than expected.
Workaround:
None identified.
Status:
For the steppings affected, see the Summary Tables of Changes.
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