33
Specification Update
AAN53.
Memory Aliasing of Code Pages May Cause Unpredictable System
Behavior
Problem:
The type of memory aliasing contributing to this erratum is the case where two
different logical processors have the same code page mapped with two different
memory types. Specifically, if one code page is mapped by one logical processor as
write-back and by another as uncachable and certain instruction fetch timing conditions
occur, the system may experience unpredictable behavior.
Implication:
If this erratum occurs the system may have unpredictable behavior including a system
hang. The aliasing of memory regions, a condition necessary for this erratum to occur,
is documented as being unsupported in the
Intel 64 and IA-32 Intel
®
Architecture
Software Developer's Manual, Volume 3A
, in the section titled
Programming the PAT
.
Intel has not observed this erratum with any commercially available software or
system.
Workaround:
Code pages should not be mapped with uncacheable and cacheable memory types at
the same time.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN54.
Performance Monitor Counters May Count Incorrectly
Problem:
Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H - C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication:
The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround:
Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished
by first disabling, saving valid events and clearing from the select registers, then
programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the
IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and
restoring previous programming if necessary. Each performance counter, IA32_PMCx,
must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of
the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits
[3:0]. All three values must be written to either the same or different
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN55.
Processor Forward Progress Mechanism Interacting With Certain
MSR/CSR Writes May Cause Unpredictable System Behavior
Problem:
Under specific internal conditions, a mechanism within the processor to ensure forward
progress may interact with writes to a limited set of MSRs/CSRs and consequently may
lead to unpredictable system behavior.
Implication:
This erratum may cause unpredictable system behavior.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
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