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Specification Update
AAN81.
PECI MbxGet() Commands May Fail Several Times Before Passing
When Issued During Package C6
Problem:
PECI (Platform Environment Control Interface) MbxSend() requests may become
blocked when the processor is in package C6. This temporary blocking may cause
subsequent MbxGet() commands to result in the receipt of a bad write FCS (frame
checksum).
Implication:
Due to this erratum, as long as the host retries the MbxGet() command the results will
be delivered upon the subsequent exit from package C6, but this may take several
milliseconds depending on the platform or operating system.
Workaround:
PECI MbxGet() commands may need to be retried several times before successful
completion.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN82.
VM Exits Due to EPT Violations Do Not Record Information About Pre-
IRET NMI Blocking
Problem:
With certain settings of the VM-execution controls VM exits due to EPT violations set bit
12 of the exit qualification if the EPT violation was a result of an execution of the IRET
instruction that commenced with non-maskable interrupts (NMIs) blocked. Due to this
erratum, such VM exits will instead clear this bit.
Implication:
Due to this erratum, a virtual-machine monitor that relies on the proper setting of bit
12 of the exit qualification may deliver NMIs to guest software prematurely.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN83.
Intel® VT-d Receiving Two Identical Interrupt Requests May Corrupt
Attributes of Remapped Interrupt or Hang a Subsequent Interrupt-
Remap-Cache Invalidation Command
Problem:
If the Intel® VT-d (Intel® Virtualization Technology for Directed I/O) interrupt-
remapping hardware receives two identical back-to-back interrupt requests, then the
attributes of the remapped interrupt returned may be corrupted. This interrupt
sequence may also hang the system if the software executes a subsequent interrupt-
remap-cache invalidation command.
Implication:
This scenario may lead to unpredictable external interrupt behavior; or a subsequent
interrupt-remap-cache invalidation command submitted by software may hang.
Workaround:
A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Workaround:
Status:
For the steppings affected, see the Summary Tables of Changes.
AAN84.
S1 Entry May Cause Cores to Exit C3 or C6 C-State
Problem:
Under specific circumstances, S1 entry may cause a logical processor to spuriously
wake up from C3 or C6 and transition to a C0/S1 state. Upon S1 exit, these logical
processors will be operating in C0.
Implication:
In systems where S1 is used for power savings, customers may observe higher S1
power than expected and software may observe a different C-state on S1 exit than on
S1 entry.
Workaround:
It possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the Summary Tables of Changes.
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